View SC28L202A1B_1260775.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sc28l202 dual universal asynchronous receiver/transmitter (duart) objective specification supersedes data of 2000 jan 31 ic19 data handbook 2000 feb 10 integrated circuits
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 i description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin configuration for 80xxx bus interface (intel) (preliminary 2/10/00) 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . configuration for 68xxx bus interface (motorola) 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . overall description 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . brief description of functional blocks 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus interface 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing circuits 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/o ports 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uarts 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmitters and receivers 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . character and address recognition 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flow control 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test modes and software 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . detailed descriptions 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus interface 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing circuit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/o ports 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uart operation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receiver operation 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . arbitrating interrupt structure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming the host interface 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register description and programming note 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers that control global properties of the 28l202 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gccr global configuration control register 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gccr(7:6) dackn assertion 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gccr(5:3): reserved 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gccr(2:1): interrupt vector configuration 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gccr(0): interrupt status masking 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sfsr a and b special feature & status register 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sfsr(7:4) reserved 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sfsr(3) status of loop back error check. 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sfsr(0) reserved 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . trr test and revision register. 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . trr(7) test 2 enable 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . trr [6:0] chip revision code 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stcr scan test control register. 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ses system enable status register, a and b 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eos enhanced operation status register 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uart registers 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . these registers are generally concerned with formatting, transmitting and receiving data. 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr0 mode register 0, a and b 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr0[7] fixed length watchdog timer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr0[5:4] tx interrupt fill level. 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr0[3] fifo size 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr0[2:0] legacy baud rate group selection 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 mode register 1, a and b 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1[7] receiver request to send (hardware flow control) 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1[6] receiver interrupt control bit 1. 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 [5] error mode select and sub modes 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1[4:3] parity mode select 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1[2] parity type select 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1[1:0] bits per character select 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2 mode register 2, a and b 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[7:6] mode select 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[7:6] = b'00 normal mode 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[7:6] = b'01 automatic echo 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[7:6] = b'10 selects local loop back diagnostic mode. in this mode: 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2 [7:6] = b'11 selects the remote loop back diagnostic mode. in this mode: 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[5] transmitter request to send control 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[4] clear to send control 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2[3:0] stop bit length select 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 ii mr3 mode register 3, a and b 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr3[7 & 6] xon/xoff character stripping 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr3[5:4] reserved 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr3[3:2] xon/xoff processing 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr3[1:0] address recognition 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rxcsr receiver clock select register a and b 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . txcsr transmitter clock select register a and b 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx and tx clock select table 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . crx command register extension, a and b 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cr[7] lock tx and rx enables. 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . writes to the lower 5 bits of the cr would usually have cr[7] 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cr[6] enable transmitter 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cr[5] enable receiver 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cr[4:0] miscellaneous commands (see table below) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . command register extension table a and b 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr channel status register a and b 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[7] received break 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[6] framing error (fe) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[5] parity error (pe) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[4] overrun error (oe) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr [3] transmitter idle (tx idle) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[2] transmitter ready (txrdy) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[1] rxfifo full (rxfull) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr[0] receiver ready (rxrdy) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr interrupt status register a and b 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[7] input change of state. 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[6] fixed watchdog timeout. 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[5] address recognition status change. 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[4] xon/xoff status change. 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[3] counter timer status 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[2] change in channel break status. 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[1] rxint. (also rx dma hand shake at i/o pins) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[0] txint. (also tx dma hand shake at i/o pins) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr interrupt mask register a and b 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[7] cos enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[6] fixed watchdog enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[5] address recognition enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[4] xon/xoff enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[3] counter/timer enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[1] receiver (rx) enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr[0] transmitter (tx) enable 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rxfifo receiver fifo, a and b 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . txfifo transmitter fifo, a and b 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rxfil receiver fifo interrupt level, a and b 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rxfl receiver fifo fill level register 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . txfil transmitter fifo interrupt level a and b 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . txel transmitter fifo empty level register 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers for character recognition 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xoncr xon/xoff character register a and b 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xoffcr xoff character register a and b 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . arcr address recognition character register a and b 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xisr xonxoff interrupt status register a and b (reading this register clears xisr(7:4)) 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xisr[7:6] received x character status. 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xisr[5:4] automatic transmission status. 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xisr[3:2] txd condition of the automatic flow control status. 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xisr[1:0] txd x character status. 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . wcxer watch dog, character, address and x enable register a and b 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmable counters, timers and baud rate generators 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pbrgpu programmable brg timer reload registers, upper 0 and 1 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pbrgpl programmable brg timer reload registers, lower 0 and 1 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctcs 0 and 1 counter timer clock source 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctvu counter timer value registers, upper 0 and 1 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctvl counter timer value registers, lower 0 and 1 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pbrgcs programmable brg clock source 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctpu counter timer preset upper 0 and 1 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctpl counter timer preset low 0 and 1 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 iii registers of the arbitrating interrupt system and bidding control 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . icr interrupt control register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ucir update cir 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cir current interrupt register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivr interrupt vector register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . modification of the ivr 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gicr global interrupting channel register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gibcr global interrupting byte count register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gitr global interrupting type register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . grxfifo global rxfifo register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gtxfifo global txfifo register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcrbrk bidding control register break change, a and b 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcrcos bidding control register change of state, a and b 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcrx bidding control register xon/xoff, a and b 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcra bidding control register address, a and b 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr c/t bidding control register c/t, 0 and 1 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcrlbe bidding control register received loop back error 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers of the i/o ports 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipcrl input port change register lower nibble, a and b (n = a for a, n = b for b) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipcru input port change register upper nibble, a and b (n = a for a, n = b for b) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipr input port register, a and b (n = a for a, n = b for b) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipce input change detect enable, a and b (n = a for a, n = b for b) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/opcr 0 i/o port configuration register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/opcr 1 i/o port configuration register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/opcr 2 i/o port configuration register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/opcr 3 i/o port configuration register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sopr a and sopr b set the output port bits (opr a and opr b) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ropr a and ropr b reset ropr output port bits (opr a and opr b) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . opr output port register, a and b (n = a for a, n = b for b) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . the registers for compatibility with previous duarts 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register descriptions mode registers 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 mode register 1 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 a[7] channel a receiver requesttosend control (flow control) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1[6] receiver interrupt control bit 1. see description under mr0[6]. 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 a[5] channel a error mode select 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 a[4:3| channel a parity mode select 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 a[2] channel a parity type select 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr1 a[1:0] channel a bits per character select 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mr2 mode register 2 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[7] received break 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[6] channel a framing error 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[5] channel a parity error 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[4] channel a overrun error 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[3] channel a transmitter empty (txemt a) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[2] channel a transmitter ready (txrdy a) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[1] channel a fifo full (ffull a) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr a[0] channel a receiver ready (rxrdy a) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sr b channel b status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr a channel a clock select register csr a [7:4] channel a receiver clock select 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr clock select register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr a [3:0] channel a external transmitter clock select 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr b [7:4] channel b receiver clock select 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr b [3:0] channel b transmitter clock select 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx fifo register. for characters shorter than 8 bits the unused bits are set to zero 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tx fifo register. for characters shorter than 8 bits the unused bits are set to zero 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cr a and b command register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cr command register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . command register table a and b 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipcr input port configuration register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipcr [7:4] i/03a, i/o2 a, i/o1 a, i/o0 a changeofstate 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ipcr [3:0] i/o3 a, i/o2 a, i/o1 a, i/o0 a logical level of i/o pin. 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acr auxiliary control register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acr[7] baud rate generator set select 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acr[6:4] counter/timer mode and clock source select 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acr [3:0] i/o3 a, i/o2 a, i/o1 a, i/o0 a changeofstate interrupt enable 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 iv isr interrupt status register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[7] input port change status 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[6] channel b change in break 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[5] rx b interrupt 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[4] tx b interrupt 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[3] counter ready. 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[2] channel a change in break 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[1] rx a interrupt 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isr[0] tx a interrupt 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . imr interrupt mask register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctpu counter timer preset upper (counter/timer 0) 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctpl counter timer preset lower (counter/timer 0) 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctvu counter timer value upper (counter/timer 0) 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctvl counter timer value lower (counter/timer 0) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivr interrupt vector register in 68k mode and general purpose read write register in the x86 mode 49 . . . . . . . . . . . . . . . . . . . . . . . . . ipr input port register i/o(6:0) a 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . opcr output port configuration register. controls [7:2] b 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sopr set bits in the opr 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ropr reset bits in the opr 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . opr output port register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register maps 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register map detail (based on 28l92) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register map 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register map (based on 28l92) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register map (based on 28l92) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register map (based on 28l92) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings1 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc electrical characteristics123 (nominal 5 volts) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac characteristics1,2,3 (nominal 5 volts) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc electrical characteristics1,2,3 (nominal 3.3 volts) 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac characteristics1,2,3 (nominal 3.3 volts) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 v list of figures figure 1. reset timing (80xxx mode) 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 2. bus timing (80xxx mode) 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 3. reset timing (68xxx mode) 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 4. bus timing (read cycle) (68xxx mode) 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 5. bus timing (write cycle) (68xxx mode) 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 6. interrupt cycle timing (68xxx mode) 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7. port timing 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 8. interrupt timing (80xxx mode) 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 9. clock timing 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 10. transmitter external clocks 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11. receiver external clock 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 12. transmitter timing 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13. receiver timing 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 14. wake-up mode 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15. test conditions on outputs 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table 1. interrupt values 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 2. sc28l202 register bit descriptions 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 3. receiver fifo interrupt fill level mr0(3)=0 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 4. receiver fifo interrupt fill level mr0(3)=1 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 5. transmitter fifo interrupt fill level mr0(3)=0 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 6. transmitter fifo interrupt fill level mr0(3)=0 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 7. sc28l92 register addressing read (rdn = 0) write (wrn = 0) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 8. baud rate generator characteristics 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 9. receiver fifo interrupt fill level mr0(3)=0 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 10. receiver fifo interrupt fill level mr0(3)=1 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 11. transmitter fifo interrupt fill level mr0(3)=0 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 12. transmitter fifo interrupt fill level mr0(3)=1 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 13. baud rate (base on a 14.7456 mhz crystal clock) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 14. acr 6:4 field definition 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors objective specification sc28l202 dual uart 1 2000 feb 10 description the 28l202 is a high performance dual uart. its functional and programming features closely match but greatly extend those of previous philips dual channel uarts. its configuration on power up is similar that of the sc26c92. its differences from the sc26c92 are: 256character receiver, 256 character transmit fifos, 3 and 5 volt compatibility, 8 i/o ports for each uart 16 total, arbitrating interrupt system and overall faster buss and data speeds. it is fabricated in an advanced 0.5 micron cmos process that allows stand by current of less that 10 microamperes. it is a member of the impact ? line of data communications parts pin or register programming will allow the device to operate with either the motorola or intel bus interface by changing the function of some pins (reset is inverted, dackn, and iackn enabled for example). the philips semiconductors 28l202 dual universal asynchronous receiver/transmitter (duart) is a singlechip cmoslsi communications device that provides two fullduplex asynchronous receiver/transmitter channels in a single package. it interfaces directly with microprocessors and may be used in a polled or interrupt driven system. the use of the interrupt system provides intelligent interrupt vectors. the operating mode and data format of each channel may be programmed independently. additionally, each receiver and transmitter can select its operating speed as one of twentyseven fixed baud rates; a 16x clock derived from one of two programmable counter/timers, or an external 1x or 16x clock. the baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. the ability to independently program the operating speed of the receiver and transmitter make the duart particularly attractive for dualspeed channel applications such as clustered terminal systems and bridges. each receiver and transmitter is buffered by 256 character fifos to nearly eliminate the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. in addition, a flow control capability (xon/xoff and rts/cts) is provided to disable a remote transmitter when the receiver buffer is full. also provided on the 28l202 is a multipurpose 8bit i/o for each channel. these can be used as generalpurpose i/o ports or can be assigned specific functions (such as clock inputs or status and interrupt outputs) under program control. normally they will be used for modem control and dma interface. all ports have change of state detectors and input sections are always active making output signals available to the internal circuits and the control processor. the 28l202 are available in 52pin plastic quad flat pack (pqfp), or 56-pin tssop packages. features ? member of impact family: 3.3 to 5.0 volt , 40 c to +85 c and 68k for 80xxx bus interface for all devices. ? dual fullduplex independent asynchronous receiver/transmitters ? 256 character fifos for each receiver and transmitter ? powers up to 9600 baud, 1 stop bit, no parity, 1 stop bit, interrupt disabled, all i/o set to input. ? pin programming to 68k or 80xxx bus interface ? three character recognition system per channel, used as: general purpose character recognition xon/xoff character recognition address recognition wake up (multidrop or a9 bito) mode system provides 4 levels of automation on a recognition event ? programmable data format 5 to 8 data bits plus parity and 9 bit mode odd, even, no parity or force parity 9/16,1, 1.5 or 2 stop bits ? 16bit programmable counter/timer ? programmable baud rate for each receiver and transmitter selectable from: 27 fixed rates: 50 to 2.0 meg baud (includes middi ? rate) other baud rates via external clocks and c/t programmable userdefined rates derived from a programmable counter/timer external 1x or 16x clock ? parity, framing, and overrun error detection ? false start bit detection ? line break detection and generation ? programmable channel mode normal (fullduplex) automatic echo local loop back remote loop back multidrop mode (also called `wakeup' or `9bit') ? multifunction 8 bit i/o input port per channel loosely assigned to each channel. can serve as clock or control inputs change of state detection on eight inputs inputs have typically >100mohm pullup resistors modem and dma interface ? versatile arbitrating interrupt system interrupt system totally supports `single query' polling output port can be configured to provide a total of up to six separate interrupt type outputs that may be wire ored (switched to open drain). each fifo can be independently programmed for any of 256 interrupt levels watch dog timer for each receiver ? maximum data transfer rates: 1x 3 mb/sec, 16x 2 mb/sec ? automatic wakeup mode for multidrop applications ? startend break interrupt/status ? detects break which originates in the middle of a character ? onchip crystal oscillator ? power down mode at less than 10 m a ? receiver timeout mode ? single +3.3v or +5v power supply
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 2 ordering information diti industrial di description (preliminary as of 1/31/00) v cc = +3.3 +5v 10%, drawing number (preliminary as of 1/31/00) t amb = 40 c to +85 c n u mber 52-pin plastic quad flat pack (pqfp) SC28L202A1B sot379-1 56-pin tssop sc28l202a1d sot364-1
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 3 pin configuration for 80xxx bus interface (intel) (preliminary 2/10/00) symbol pin type name and function i/m i bus configuration: when high or not connected configures the bus interface to the conditions shown in this table. d0d7 i/o data bus: bidirectional 3state data bus used to transfer commands, data and status between the duart and the cpu. d0 is the least significant bit. cen i chip enable: activelow input signal. when low, data transfers between the cpu and the duart are enabled on d0d7 as controlled by the wrn, rdn and a6a0 inputs. when high, places the d0d7 lines in the 3state condition. wrn i write strobe: when low and cen is also low, the contents of the data bus is loaded into the addressed register. the transfer occurs on the rising edge of the signal. rdn i read strobe: when low and cen is also low, causes the contents of the addressed register to be presented on the data bus. the read cycle begins on the falling edge of rdn. a6a0 i address inputs: select the duart internal registers and ports for read/write operations. reset i reset: a high level clears internal registers (sr a, sr b, imr, isr, opr, opcr), places i/o[7:0] a and b at high impedance input state, stops the counter/timer, and puts channels a and b in the inactive state, with the txd a and txd b outputs in the mark (high) state. sets mr pointer to mr1 9600 baud, 1 start, no parity and 1 stop bit(s). (see reset table) irqn o interrupt request: activelow, opendrain, output which signals the cpu that one or more of the eighteen (18) maskable interrupting conditions are true. x1 / sclk i crystal 1: crystal or external clock input. a crystal or clock of the specified limits must be supplied at all times. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 9). x2 o crystal 2: connection for other side of the crystal. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 9). if x1/sclk is driven from an external source, this pin must be open or not driving more that 2 cmos or ttl loads. rxd a i channel a receiver serial data input: the least significant bit is received first. amarko is high; aspaceo is low. rxd b i channel b receiver serial data input: the least significant bit is received first. amarko is high; aspaceo is low. txd a o channel a transmitter serial data output: the least significant bit is transmitted first. this output is held in the amarko condition when the transmitter is disabled, idle or when operating in local loop back mode. amarko is high; aspaceo is low. txd b o channel b transmitter serial data output: the least significant bit is transmitted first. this output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `mark' is high; `space' is low. i/o[7:0]a i/o generalpurpose input and output ports channel a: the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. these pins are set to input only when addressed from the low order 16 address space. when these pins are configured for interrupt type signals (rxrdy, txrdy, c/trdy) they switch to open drain outputs. i/o[7:0}b i/o generalpurpose input and output ports channel b: the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. these pins are set to output only when addressed from the low order 16 address space. when these pins are configured for interrupt type signals (rxrdy, txrdy, c/trdy) they switch to open drain outputs. vcc power power supply: +3.3 or +5v supply input 10% (4 pins). operation is assured from 2.97 to 5.5 volts. timing parameters are specified with respect to the vcc being at 3.3 of 5.0 volts +/ 10% gnd power ground (5 pins)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 4 configuration for 68xxx bus interface (motorola) symbol pin type name and function i/m i bus configuration: when low configures the bus interface to the conditions shown in this table. d0d7 i/o data bus: bidirectional 3state data bus used to transfer commands, data and status between the duart and the cpu. d0 is the least significant bit. csn i chip enable: activelow input signal. when low, data transfers between the cpu and the duart are enabled on d0d7 as controlled by the r/wn and a0a6 inputs. when high, places the d0d7 lines in the 3state condition. r/wn i read/write: input signal. when csn is low r/wn high input a read cycle, when low a write cycle. iackn i interrupt acknowledge: active low input indicates an interrupt acknowledge cycle. usually asserted by the cpu in response to an interrupt request. when asserted places the interrupt vector on the bus and asserts dackn. dackn o data transfer acknowledge: a 3state active low output asserted in a write, read, or interrupt acknowledge cycle to indicate proper transfer of data between the cpu and the duart. a6a0 i address inputs: select the duart internal registers and ports for read/write operations. resetn i reset: a low level clears internal registers (sr a , sr b, imr, isr, opr, opcr), places i/o[7:0] a and b at high impedance input state, stops the counter/timer, and puts channels a and b in the inactive state, with the txd a and txd b outputs in the mark (high) state. sets mr pointer to mr1, 9600 baud, 1 start, no parity and 1 stop bit(s). (see reset table) irqn o interrupt request: activelow, opendrain, output which signals the cpu that one or more of the eighteen (18) maskable interrupting conditions are true. x1 / sclk i crystal 1: crystal or external clock input. a crystal or clock of the specified limits must be supplied at all times. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 9). x2 o crystal 2: connection for other side of the crystal. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 9) . if sclk is driven from an external source, this pin must be left open. rxd a i channel a receiver serial data input: the least significant bit is received first. amarko is high; aspaceo is low. rxd b i channel b receiver serial data input: the least significant bit is received first. amarko is high; aspaceo is low. txd a o channel a transmitter serial data output: the least significant bit is transmitted first. this output is held in the amarko condition when the transmitter is disabled, idle or when operating in local loop back mode. amarko is high; aspaceo is low. txd b o channel b transmitter serial data output: the least significant bit is transmitted first. this output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `mark' is high; `space' is low. i/o[7:0]a i/o generalpurpose input and output ports channel a: the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. these pins are set to input only when addressed from the low order 16 address space. when these pins are configured for interrupt type signals (rxrdy, txrdy, c/trdy) they switch to open drain outputs. i/o[7:0}b i/o generalpurpose input and output ports channel b: the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. these pins are set to output only when addressed from the low order 16 address space. when these pins are configured for interrupt type signals (rxrdy, txrdy, c/trdy) they switch to open drain outputs vcc power power supply: +3.3 or +5v supply input 10% (4 vcc pins) ). operation is assured from 2.97 to 5.5 volts. timing parameters are specified with respect to the vcc being at 3.3 of 5.0 volts +/ 10% vss power ground (5 vss pins)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 5 28l202 pin configurations pin function pin function 1 vcc 29 cen 2 vss 30 wrn 3 a6 31 rdn 4 a5 32 txdb 5 a4 33 i/o7b 6 a3 34 i/o6b 7 rxda 35 i/o5b 8 reset 36 i/o4b 9 d7 37 i/o3b 10 d6 38 i/o2b 11 d5 39 i/o1b 12 d4 40 i/o0b 13 vcc 41 vcc 14 nc 42 vcc 15 vss 43 vss 16 vss 44 vss 17 d3 45 i/o7a 18 d2 46 i/o6a 19 d1 47 i/o5a 20 d0 48 i/o4a 21 i / m 49 i/o3a 22 rxdb 50 i/o2a 23 a2 51 i/o1a 24 a1 52 i/o0a 25 a0 53 txda 26 (iackn) 54 irqn 27 vcc 55 x1 / sclk 28 vss 56 x2 80xxx 56 pin tssop 68xxx 56 pin tssop pin function pin function 1 vcc 29 cen 2 vss 30 rwn 3 a6 31 dackn 4 a5 32 txdb 5 a4 33 i/o7b 6 a3 34 i/o6b 7 rxda 35 i/o5b 8 resetn 36 i/o4b 9 d7 37 i/o3b 10 d6 38 i/o2b 11 d5 39 i/o1b 12 d4 40 i/o0b 13 vcc 41 vcc 14 nc 42 vcc 15 vss 43 vss 16 vss 44 vss 17 d3 45 i/o7a 18 d2 46 i/o6a 19 d1 47 i/o5a 20 d0 48 i/o4a 21 i / m 49 i/o3a 22 rxdb 50 i/o2a 23 a2 51 i/o1a 24 a1 52 i/o0a 25 a0 53 txda 26 iackn 54 irqn 27 vcc 55 x1 / sclk 28 vss 56 x2 sd00691
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 6 52 pin pqfp 15 16 17 18 19 20 21 22 23 24 14 25 26 51 50 49 48 47 46 45 44 43 42 52 41 40 37 36 35 34 33 32 31 30 29 28 27 39 38 3 4 5 6 7 8 9 10 11 12 13 1 2 pin function pin function 1 rxda 27 i/o5b 2 reset 28 i/o4b 3 d7 29 i/o3b 4 d6 30 i/o2b 5 d5 31 i/o1b 6 d4 32 i/o0b 7 vcc 33 vcc 8 vss 34 vss 9 d3 35 i/o7a 10 d2 36 i/o6a 11 d1 37 i/o5a 12 d0 38 i/o4a 13 i / m 39 i/o3a 14 rxdb 40 i/o2a 15 a2 41 i/o1a 16 a1 42 i/o0a 17 a0 43 txda 18 (iackn) 44 irqn 19 vcc 45 x1 / sclk 20 vss 46 x2 21 cen 47 vcc 22 wrn 48 vss 23 rdn 49 a6 24 txdb 50 a5 25 i/o7b 51 a4 26 i/o6b 52 a3 28l202 pin configuration sd00692 80xxx 52 pin pqfp 68xxx 52 pin pqfp pin function pin function 1 rxda 27 i/o5b 2 resetn 28 i/o4b 3 d7 29 i/o3b 4 d6 30 i/o2b 5 d5 31 i/o1b 6 d4 32 i/o0b 7 vcc 33 vcc 8 vss 34 vss 9 d3 35 i/o7a 10 d2 36 i/o6a 11 d1 37 i/o5a 12 d0 38 i/o4a 13 i / m 39 i/o3a 14 rxdb 40 i/o2a 15 a2 41 i/o1a 16 a1 42 i/o0a 17 a0 43 txda 18 iackn 44 irqn 19 vcc 45 x1 / sclk 20 vss 46 x2 21 cen 47 vcc 22 rwn 48 vss 23 dackn 49 a6 24 txdb 50 a5 25 i/o7b 51 a4 26 i/o6b 52 a3
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 7 overall description the sc28l202 is composed of several functional blocks. they are listed in the approximate order of hierarchy as seen from the pins of the device. ? bus interface. 68k or x86 format ? timing circuits ? i/o ports ? uarts ? transmitters and receivers ? fifo structures ? arbitrating interrupt structure ? character & address recognition ? flow control ? test and software compatibility with previous philips (signetics) uarts brief description of functional blocks bus interface the two basic modes of bus interface the bus interface operates in a68ko or ax86o format as selected by the i/m pin. the signals used by this section are the address, data bus, chip select, read/write, data acknowledge and interrupt acknowledge and interrupt request. assertion of dackn requires two edges of the sclk after the assertion of cen. the default mode is the x86 mode. pin or register programming may change it to he 68k mode timing circuits crystal oscillator the crystal oscillator is the main timing element for the 28l202. it is nominally set at 14.7456 mhz. operation with a crystal as a frequency standard is specified from 7 mhz to 16.2 mhz the use of an external clock allows all frequencies to 50 mhz. clock prescalers are provided to match various available system clocks to those needed for baud rate generation. note : if an external clock is used x2 should not drive more than 2 cmos or 2 ttl equivalents. fixed rate brg the brg is the baud rate generator, is driven by the x1/sclk input through a programmable prescale divider. it generates all of the 27 afixedo internal baud rates. this baud rate generator is designed to generate the industry standard baud rates from a 14.7456 mhz crystal or clock frequency. x1/sclk frequencies different from 14.7456 mhz will cause the afixedo baud rates to change by exactly the ratio of 14.7456 to the different frequency. countertimer the two countertimers are programmable 16 bit adowno counters. it provides miscellaneous baud rates, timing periods and acts as an extra watchdog timer for the receivers. it has 8 programmable clock sources derived from internal and external signals. it may also act as a character counter for the receiver. interrupts from the counter timer are generated as it passes through zero. programmable brg (pbrg) this is another 16 bit programmable counter to generate only baud rates or miscellaneous clock frequencies. its output is available to the receivers and transmitters and may be delivered to i/o ports. it has 8 programmable clock sources derived from internal and external signals. i/o ports the sc28l202 is provided with 16 i/o ports. these ports are true input and/or output structures and are equipped with a change of state detector. the input circuit of these pins is always active. under program control the ports my display internal signals or static logic levels. the functions represented by the i/o ports include hardware flow control. modem signals, signals for interrupt conditions or various internal clocks and timing intervals. noisy inputs to the i/o ports are filtered (debounced) by a 38.4 khz clock. change of state detectors are provided for each pin and are always available. uarts the uarts are fully independent, full duplex and provide all normal asynchronous functions: 5 to 8 data bits, parity odd or even, programmable stop bit length, false start bit detection. also provided are 256 byte fifos xon/xoff software flow. the brg, countertimer, or external clocks provide the baud rates. the receivers and transmitters may operate in either the a1xo or a16xo modes. the control section recognizes two address schemes. one is the subset of the other: a four (4) bit and an eight (7) bit address spaces. the purpose of this is to provide a large degree of software compatibility with previous philips/signetics uarts. transmitters and receivers the transmitters and receivers are independent devices capable of full duplex operation. baud rates, interrupt and status conditions are under separate control. transmitters have automatic simplex aturnaroundo. receivers have rts and xon/xoff flow control and a three character recognition system. fifo structures the fifo structure is 256 bytes for each of the four fifos in the duart. they are organized as 11 bit words for the receiver and 8 bye words for the transmitter. the interrupt level may be set at any value from 0 to 255. the interrupt level is independently set for each fifo. fifo interrupt and dma fill/empty levels are controlled by the rxfil and txfil registers which may set any level of the from 0 to 255. the signals associated with the fifo fill levels are available to the i/o pins (for interrupt or dma) and to the arbitrating interrupt system for afine tuningo of the arbitration authority. intelligent interrupt arbitration the interrupt system uses a highly programmable arbitrating technique to establish when an interrupt should be presented to the processor. the advantageous feature of this system is the presentation of the context of the interrupt. it is presented in both a current interrupt register and in the interrupt vector. the context of the interrupt shows the interrupting channel, identifies which of the 18 possible sources in requesting interrupt service and in the case of a receiver or transmitter gives the current fill level of the fifo. the content of the current interrupt register also drives the global registers of the interrupt system. these registers are indirect addresses (pointers) to the interrupt source requesting service. programming of bid control registers allows the interrupt level of any source to be varied at any time over a range of 256 levels. character and address recognition the character recognition system is designed as a generalpurpose system. there is one for each uart. each recognition block stores
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 8 up to three characters. the recognition is done on a byte boundary and sets status and interrupt when recognition events occur. three modes of automatic operation are provided for the inband flow control and three modes of automatic operation are provided for address recognition. both inband flow control and address recognition may also be completely under the control of the host processor. a subset of the recognition system is xon/xoff character recognition and the recognition of the multidrop address character. if xon/xoff or multidorp function is enabled the recognition system passes the information about the recognition event to the appropriate receiver or transmitter state machine for execution. in any case the information about a recognition event is available to the interrupt system and to the control processor. flow control flow control is implemented in either the traditional rts/cts protocol or in the ainboundo xon/xoff method. both may be controlled by fully/partially automatic methods or by interrupt generation. test modes and software four test modes are provided to verify uart function and processor interface integrity. the first three are auto echo, local loop back, and remote loop back. through local loop back the software developer may verify all of the interrupt, flow control; the hardware designer verify all of the timing and pin connections. this information is obtained without any recourse to external test equipment, logic analyzers or terminals. the fourth, receiver error loop back verification, employs a method of automatic checking (accounting for transmission delays) of the transmitted data to as echoed back through the remote receiver. errors generate interrupt and status events. detailed descriptions note : for the convenience of the reader some paragraphs of the following sections are repeated in descriptions of closely linked functions described in other sections. bus interface the bus interface operates in two modes selected by the i/m pin. if this pin is high or left open the signals dackn signal is not generated or used and data flow to and from the chip is controlled by the state the cen, rdn, wrn pin combination. if the i/m pin is tied low the data is written to the device when the dackn pin is asserted low by the duart. read data is presented by a delay from cen active. the host interface is comprised of the signal pins cen, wrn rdn, (or r/wn) iackn, dackn, irqn, 6 address pins and 8 threestate data bus pins. addressing of the various functions of the duart is through the address bus a(6:0). data is presented on the 8bit data bus. dackn cycle when operating in the a68ko mode bus cycle completion is indicated by the dackn pin (an open drain signal) going low. the timing of dackn is by gccr(6) where two time delays area available. the delay begins with the falling edge of cen and dackn is presented after either two edges of he x1/sclk (1/2 x1/sclk cycle) or, under program control, a short internal delay of less than 50 ns. usually in this mode the address and data are set up with respect to the leading edges of the bus cycle. the dackn pin is a three state driver. at the termination of an access to the l202 a very short pulse (less than 5 ns) drives the pin high and immediately returns to the high impedance state. this will occur at the termination of the cen or iackn cycle. note : the faster x86 timing may be used in the 68k mode if the bus cycles are faster than 1/2 period of the sclk clock. withdrawing cen before dackn prevents the generation of dackn. in this case bus timing is effectively that of the x86 mode. when operating in the ax86o mode dackn is not generated. data is written on the termination of cen or wrn whichever one occurs first. read data is presented from the leading edge of the read condition (cen and rdn both low). iackn cycle, update cir when the host cpu responds to the interrupt, it will usually assert the iackn signal low. this will cause the intelligent interrupt system of the duart to generate an iackn cycle in which the condition of the interrupting source is determined. when iackn asserts, the last valid of the interrupt arbitration cycle is captured in the cir. the value captured presents all of the important details of the highest priority interrupt at the moment the iackn (or the oupdate ciro command) was asserted. due to system interrupt latency the interrupt condition captured by the cir may not be the condition that caused the initial assertion of the interrupt. the dual uart will respond to the iackn cycle with an interrupt vector. the interrupt vector may be a fixed value, the content of the interrupt vector register, or when ointerrupt vector modificationo is enabled via icr, it may contain codes for the interrupt type and/or interrupting channel. this allows the interrupt vector to steer the interrupt service directly to the proper service routine. the interrupt value captured in the cir remains until another iackn or aupdate ciro command is given to the duart. the interrupting channel and interrupt type fields of the cir set the current ointerrupt contexto of the duart. the channel component of the interrupt context allows the use of global interrupt information registers that appear at fixed positions in the register address map. for example, a read of the global rxfifo will read the channel b rxfifo if the cir interrupt context is channel b receiver. at another time read of the grxfifo may read the channel a rxfifo (cir holds a channel a receiver interrupt) and so on. global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from fifos without explicitly addressing them. the cir will load with 0x00 if iackn or update cir is asserted when the arbitration circuit is not asserting an interrupt. in this condition there is no arbitration value that exceeds the threshold value. when interrupt vector modification is active in this situation the interrupt vector bits associated with the cir will all be zero. a zero type field indicates nothing with in the duart is requiring processor service. note : iackn is essentially a special read action where the value of the interrupt vector is presented to the data bus. timing circuit crystal oscillator the crystal oscillator operates directly from a crystal, tuned between 7.0 mhz and 16.2 mhz connected across the x1/sclk and x2 inputs with a minimum of external components. brg values listed for the clock select registers correspond to a 14.7456 mhz crystal frequency. use of different frequencies will change the astandardo baud rates by precisely the ratio of 14.7456 mhz to the different crystal frequency. an external clock up to 50 mhz frequency range may be connected to x1/sclk pin. if an external clock is used instead of a crystal, x1/sclk must be driven and x2 left floating or driving a load of not
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 9 more than 2 cmos or ttl equivalents. the x1/sclk clock serves as the basic timing reference for the baud rate generator (brg) and is available to the programmable brg (pbrg), countertimers, control logic and the uart receivers and transmitters. baud rate generator brg the baud rate generator operates from the oscillator or external x1/sclk clock input and generates 27 commonly used data communications baud rates (including middi) ranging from 50 to 921.6k baud. these common rates may be increased (up to 3000k baud) when faster clocks are used on the x1/sclk clock input. (see receiver and transmitter clock select register descriptions.) all of these are available simultaneously for use by any receiver or transmitter. the clock outputs from the brg are at 16x the actual baud rate. please see counter timer description for a description of the frequency error that the asynchronous protocol may tolerate. depending on character length it varies from 4.1% to 6.7%. countertimer the two counter/timers are programmable 16 bit dividers that are used for generating miscellaneous clocks or generating timeout periods. these clocks may be used by any or all of the receivers and transmitters in the duart or may be directed to an i/o pin for miscellaneous use. counter/timer programming the counter timer is a 16bit programmable divider that operates in one of four modes: character count, counter, timer, and time out. character count counts characters. the timer mode generates a square wave. in the counter mode it generates a time delay. in the time out mode it monitors the time between received characters. the c/t uses the numbers loaded into the counter/timer lower register (ctpl) and the counter/timer upper register (ctpu) as its divisor. the counter timer is controlled with six commands: start/stop c/t, read/write counter/timer lower register and read/write counter/timer upper register. these commands have slight differences depending on the mode of operation. please see the detail of the commands under the ctpl/ctpu register descriptions. whenever the these timers are selected via the receiver or transmitter clock select register their output will be configured as a 16x clock for the respective receiver or transmitter. therefore one needs to program the timers to generate a clock 16 times faster than the data rate. the formula for calculating 'n', the number loaded to the ctpu and ctpl registers, based on a particular input clock frequency is shown below. for the timer mode the formula is as follows: n clockinputfrequency (2 16 (baud rate desired)) note : `n' may assume a value of 1. in previous philips data communications controllers this value was not allowed. the counter/timer clock select register (ctcs) controls the counter/timer input frequency. the frequency generated from the above formula will be at a rate 16 times faster than the desired baud rate. the transmitter and receiver state machines include divide by 16 circuits, which provide the final frequency and provide various timing edges used in the qualifying the serial data bit stream. often this division will result in a noninteger value: 26.3 for example. one may only program integer numbers to a digital divider. there for 26 would be chosen. if 26.7 were the result of the division then 27 would be chosen. this gives a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error of 1.14% or 1.12% respectively, well within the ability of the asynchronous mode of operation. higher input frequency to the counter reduces the error effect of the fractional division one should be cautious about the assumed benign effects of small errors since the other receiver or transmitter with which one is communicating may also have a small error in the precise baud rate. in a ocleano communications environment using one start bit, eight data bits and one stop bit the total difference allowed between the transmitter and receiver frequency is approximately 4.6%. less than eight data bits will increase this percentage. programmable baud rate generators. pbrg two pbrg counters (used only for random baud rate generation) the two pbrg timers are programmable 16 bit dividers that are used for generating miscellaneous clocks. these clocks may be used by any or all of the receivers and transmitters in the sc28l202 or output to the general purpose i/o pins. each timer unit has eight different clock sources available to it as described in the pbrg clock source register. note that the timer run and stop controls are also contained in this register. the pbrg counters generate a symmetrical square wave whose half period is equal in time to the division of the selected pbrg timer clock source by the number loaded to the pbrgpu and pbrgpl preset registers. thus, the output frequency will be the clock source frequency divided by twice the 16 bit value loaded to these registers. this is the result of counting down once for the high portion of the output wave and once for the low portion. whenever the these timers are selected via the receiver or transmitter clock select register their output will be configured as a 16x clock for the respective receiver or transmitter. therefore one needs to program the timers to generate a clock 16 times faster than the data rate. the formula for calculating 'n', the number loaded to the pbrgpl and pbrgpu registers, is the same as shown above i/o ports eight i/o ports are alooselyo provided for each channel. they may be programmed to be inputs or outputs. the input circuits are always active whether programmed as and input or an output. in general a 2bit code in the i/opcr (i/o port control register) controls what function these pins will present. all i/o ports default to high impedance input state on power up. when calling software written for previous philips (signetics) duarts the user should be sure to declare i/o ports to be inputs where drivers may be attached to an i/o port pin that previous software had expected to be an output. input characteristics of the i/o ports eight i/o pins are provided for each channel. these pins are configured individually to be inputs or outputs. as inputs they may be used to bring external data to the bus, as clocks for internal functions or external control signals. each i/o pin has a ochange of stateo detector. the change detectors are used to signal a change in the signal level at the pin (either 0 to 1 or 1 to 0 transitions). the level change on these pins must be stable for 25 to 50 us (two edges of the 38.4 khz baud rate clock) before the detectors will signal a valid change. these are typically used for interface signals from modems to the duart and from there to the host. output port of the i/o ports the opr, i/opcr, mr, and cr registers may control the i/o pins when configured as outputs. (for the control in the loser 16 position address space the control register is the opcr) via appropriate programming the pins of the output port may be configures as another parallel port to external circuits, or they may represent internal conditions of the uart. when this 8bit port is used as a
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 10 generalpurpose output port, the output port pins drive inverse logic levels of the individual bits in the output port register (opr). the opr register is set and reset by writing to the sopr and ropr addresses. (see the description of the sopr and ropr registers). the output pins will drive the same data polarity of the opr registers. the i/opcr (or the opcr) register conditions these output pins to be controlled by the opr or by other signals in the chip. output ports are driven high on hardware reset. uart operation receiver and transmitter the dual uart has two full duplex asynchronous receiver/transmitters. the operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter, or from an external input. registers that are central to basic fullduplex operation are the mode registers (mr0, mr1 and mr2), the clock select registers (rxcsr and txcsr), the command register (cr), the status register (sr), the transmit holding register (txfifo), the receive holding register (rxfifo), interrupt status register (isr) and interrupt mask register (imr). mr3 does not exist in 92 mode. mr3 is used in the control of the intelligent operations of the l202. transmitter status bits the sr (status register, one per uart) contains two bits that show the condition of the transmitter fifo. these bits are txrdy and tx idle. txrdy means the txfifo has space available for one or more bytes; tx idle means the txfifo is completely empty and the last stop bit has been completed the transmitter is underrun. tx idle can not be active without txrdy also being active. these two bits will go active upon initial enabling of the transmitter transmission resumes and the tx idle bit is cleared when the cpu loads at least one new character into the txfifo. the txrdy will not extinguish until the txfifo is completely full. the txrdy bit will always be active when the transmitter is enabled and there is at lease one open position in the txfifo. the transmitter is disabled by a hardware reset, a transmitter reset in the command register or by the transmitter disable bit also in the command register (cr). the transmitter must be explicitly enabled via the cr before transmission can begin. note that characters cannot be loaded into the txfifo while the transmitter is disabled, hence it is necessary to enable the transmitter and then load the txfifo. it is not possible to load the txfifo and then enable the transmission. note the difference between transmitter disable and transmitter reset. either hardware or software may cause the reset action. when reset the transmitter stops transmission immediately. the transmit data output will be driven high, transmitter status bits set to zero and any data remaining in the txfifo is effectively discarded. the transmitter disable is controlled by the tx enable bit in the command register. setting this bit to zero will not stop the transmitter immediately but will allow it to complete any tasks presently underway. it is only when the last character in the txfifo and its stop bit(s) have been transmitted that the transmitter will go to its disabled state. while the transmitter enable/disable bit in the command register is at zero the txfifo will not accept any more characters and the tx idle and txrdy bits of the status register set to zero. transmission of obreako transmission of a break character is often needed as a synchronizing condition in a data stream. the obreako is defined as a start bit followed by all zero data bits by a zero parity bit (if parity is enabled) and a zero in the stop bit position. the forgoing is the minimum time to define a break. the transmitter can be forced to send a break (continuous low condition) by issuing a start break command via the cr. once the break starts, the txd output remains low until the host issues a command to ostop breako via the cr or the transmitter is issued a software or hardware reset. in normal operation the break is usually much longer than one character time. 1x and 16x modes, transmitter the transmitter clocking has two modes: 16x and 1x. data is always sent at the 1x rate. however the logic of the transmitter may be operated with a clock that is 16 times faster than the data rate or at the same rate as the data i.e. 1x. all clocks selected internally for the transmitter (and the receiver) will be 16x clocks. only when an external clock is selected may the transmitter logic and state machine operate in the 1x mode. the 1x or 16x clocking makes little difference in transmitter operation. ( this is not true in the receiver) in the 16xclock mode the transmitter will recognize a byte in the txfifo within 1/16 to 2/16bit time and thus begin transmission of the start bit. in the 1x mode this delay may be up to 2 bit times. transmitter fifo the fifo configuration of the as 28l202 is 256 8bit words. interrupt levels may be set to any level within the fifo size and may be set differently for each fifo. logic associated with the fifo encodes the number of empty positions for presentation to the interrupt arbitration system. the encoding value is the number of empty positions. thus, an empty txfifo will bid with the value or 255; when full it will not bid at all; one position empty bids with the value 0. a full txfifo will not bid since no character is available. normally txfifo will present a bid to the arbitration system whenever it has one or more empty positions. the bits of the txfifo interrupt level in the mr0(5:4) allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, empty, 16 filled, 240 filled, full) have been reached. as will be shown later this feature may be used to make moderate improvements in the interrupt service efficiency. a similar system exists for the receiver. transmitter the 28l202 is conditioned to transmit data when the transmitter is enabled through the command register. the transmitter of the 28l202 indicates to the cpu that it is ready to accept a character by setting the isr txrdy bit in the status register. this condition can be programmed to generate an interrupt request at i/o4 or irqn. when the transmitter is initially enabled the txrdy and tx idle bits will be set in the status register. when a character is loaded to the transmit fifo the tx idle bit will be reset. the tx idle bit will not set until the transmit fifo is empty and the transmit shift register has finished transmitting the stop bit of the last character written to the transmit fifo. the txrdy bit is set whenever the transmitter is enabled and the txfifo is not full. data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. characters cannot be loaded into the txfifo while the transmitter is disabled. the transmitter converts the parallel data from the cpu to a serial bit stream on the txd output pin. it automatically sends a start bit
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 11 followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. the least significant bit is sent first. following the transmission of the stop bits, if a new character is not available in the txfifo, the txd output remains high and the tx idle bit in the status register (sr) will be set to 1. transmission resumes and the tx idle bit is cleared when the cpu loads a new character into the txfifo. if the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. the transmitter can be forced to send a continuous low condition by issuing a send break command. the transmitter can be reset through a software command. if it is reset, operation ceases immediately and the transmitter must be enabled through the command register before resuming operation. if cts option of hardware flow control is enabled (mr2 [4] = 1), the cts input at i/o0 or i/o1 must be low in order for the character to be transmitted. the transmitter will check the state of the cts input at the beginning of each character transmitted. if it is found to be high, the transmitter will delay the transmission of any following characters until the cts has returned to the low state. cts going high during the serialization of a character will not affect that character. it is an interesting point of the i/o system inputs being always active that by enabling transmitter to be sensitive the i/o0 or i/o1 and then controlling the i/o pin as an out put that one is able to control the transmitter flow via software control of the i/o pin. the transmitter can also control the rtsn outputs, i/o0 or i/o1 via mr2 [5]. when this mode of operation is set (often referred to as the rs485 method) the meaning of the i/o0 b or i/o1 b signals is aall bytes loaded to the transmitter's fifo have been transmitted including the last stop bit(s). see the mr2(5) description for enabling this automatic function. receiver operation receiver the receiver accepts serial data on the rxd pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit (if any), framing error or break condition, and presents the assembled character and its status condition to the cpu via the rxfifo. three status bits are fifoed with each character received. the rxfifo is really 11 bits wide: eight data and 3 status. unused fifo bits for character lengths less than 8 bits are set to zero. it is important to note that in the asynchronous protocol the receiver logic considers the entire message to be contained within the start bit to the stop bit. it is not aware that a message may contain many characters. the receiver returns to its idle mode at the end of each stop bit! as described below it immediately begins to search for another start bit, which is normally, of course, immediately forthcoming. 1x and 16x mode, receiver the receiver operates in one of two modes: 1x and 16x. of the two, the 16x is more robust and the preferred mode. although the 1x mode may allow a faster data rate is does not provide for the alignment of the receiver 1x data clock to that of the transmitter. this strongly implies that the 1x clock of the remote transmitter is available to the receiver; the two devices are physically close to each other. the 16x mode operates the receiver logic at a rate 16 times faster than the 1x data rate. this allows for validation of the start bit length, the validation of level changes at the receiver serial data input (rxd), and the validation of the stop bit length. of most importance in the 16x mode is the ability of the receiver logic to align the phase of the internally generated receiver 1x data clock to that of the received start bit of the remote transmitter. this occurs with an accuracy of less than 1/16 bit time. receiver the receiver of the 28l202 is conditioned to receive data when enabled through the command register. the receiver looks for a hightolow (marktospace) transition of the start bit on the rxd input pin. if a transition is detected, the state of the rxd pin is sampled each 16x clock for 71/2 clock periods (16x clock mode) or at the next rising edge of the bit time clock (1x clock mode). if rxd is sampled high, (that is the start bit was low less than 7/16 to bit time) the start bit is judged invalid and the search for another valid start bit begins immediately. if rxd is still low, a valid start bit is assumed and the receiver then continues to sample the input at onebit time intervals at the theoretical center of the bit. when the proper number of data bits and parity bit (if used) have been assembled, and one halfstop bit has been detected the receiver loads the byte to the fifo. the least significant bit is received first. the data is then transferred to the receive fifo and the isr rxrdy bit in the sr is set to a 1. this condition can be programmed to generate an interrupt at irqn or i/o[4:5] for channels a or b respectively. if the character length is less than 8 bits, the most significant unused bits in the rxfifo are set to zero. after the stop bit is detected, the receiver will immediately look for the next start bit. however, if a nonzero character was received with the stop bit at a zero level (framing error) and rxd remains low for at least another one half bit time after the stop bit was sampled, then the receiver operates as if a new start bit had been detected. it then continues assembling the next character. the error conditions of parity error, framing error, and overrun error (if any) are written to the sr at the received character boundary. this is just before the rxrdy status bit is set. a break condition is detected when rxd is low for the entire character including the parity bit, if used, and stop bit. when a break is found a character consisting of all zeros will be loaded into the rxfifo, the received break bit in the sr and the achange of breako bit in the isr are set to 1 and the receiver ready is set in the sr. the rxd input must return to high for two (2) clock edges of the rxc1x clock for the receiver to recognize the end of the break condition. at the end of the break condition the search for the next start bit begins. two edges of the rxc1x clock will usually require a high time of one rxc1x clock period or 3 rxc1x edges since the clock of the controller is usually not synchronous to nor in phase with the rxc1x clock. receiver status bits there are five (5) status bits that are evaluated with each byte (or character) received: received break, framing error, parity error, overrun error, and change of break. the first three are appended to each byte and stored in the rxfifo. the last two are not necessarily related to the byte being received or a byte that is in the rxfifo. they are however developed by the receiver state machine. the oreceived breako will always be associated with a zero byte in the rxfifo. it means that zero character was a break character and not a zero data byte. the reception of a break condition will always set the ochange of breako (see below) status bit in the interrupt status register (isr).
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 12 the change of break condition is reset by a reset error status command in the command register a framing error occurs when a nonzero character was seen and that character has a zero in the stop bit position. the parity error indicates that the receivergenerated parity was not the same as that sent by the transmitter. the framing, parity and received break status bits are reset when the associated data byte is read from the rxfifo since these aerroro conditions are attached to the byte that has the error the overrun error occurs when the rxfifo is full, the receiver shift register is full, and another start bit is detected. at this moment the receiver has 257 valid characters and the start bit of the 258 th has been seen. at this point the host has approximately 6/16 bit time to read a byte from the rxfifo or the overrun condition will be set. the 258 th character then overruns the 257 th and the 258 th the 259 th and so on until an open position in the rxfifo is seen. (aseeno meaning at least one byte was read from the rxfifo.) overrun is cleared by a use of the aerror reseto command in the command register. the fundamental meaning of the overrun is that data has been lost. data in the rxfifo remains valid. the receiver will begin placing characters in the rxfifo as soon as a position becomes vacant. note : precaution must be taken when reading an overrun fifo. there will be 256 th valid characters in the receiver fifo. there will be one character in the receiver shift register. however it will not be known if more than one aoverrunningo character has been received since the overrun bit was set. the 257 th character received and read as valid but it will not be known how many characters were lost between the two characters of the 256 th and 257 th reads of the rxfifo. in the 8-bit mode, the numbers 8 and 9 replace the numbers 256 and 257 above. the ochange of breako means that either a break has been detected or that the break condition has been cleared. this bit is available in the isr. the break change bit being set in the isr and the received break bit being set in the sr will signal the beginning of a break. at the termination of the break condition only the change of break in the isr will be set. after the break condition is detected the termination of the break will only be recognized when the rxd input has returned to the high state for two successive edges of the 1x clock; 1/2 to 1 bit time. (see above) the receiver is disabled by reset or via cr commands. a disabled receiver will not interrupt the host cpu under any circumstance in the normal mode of operation. if the receiver is in the multidrop or special mode, it will be partially enabled and thus may cause an interrupt. refer to section on wakeup and the register description for mr1 for more information. receiver fifo the receiver buffer memory is a 256 byte fifo with three status bits appended to each data byte. (the fifo is then 256 11bit owordso). the receiver state machine gathers the bits from the receiver shift register and the status bits from the receiver logic and writes the assembled byte and status bits to the rxfifo shortly after the stop bit has been sampled. logic associated with the fifo encodes the number of filled positions for presentation to the interrupt arbitration system. the encoding is always the number of filled positions. thus, a full rxfifo will bid with the value of 255 and the status register rxfull bit is set. when empty it will not bit at all. one position occupied bids with the value 1. an empty fifo will not bid since no character is available. normally rxfifo will present a bid to the arbitration system whenever it has one or more filled positions. the bits of the rxfifo interrupt offset level (rxfil) or the bits of the mr2(3:2) allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, 64 filled, 192 filled, full) have been reached. as will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. a similar system exists in the transmitter. rxfifo status bits. status reporting modes this description applies to the upper three bits in the ostatus registero these three bits are not oin the status registero; they are part of the rxfifo. the three status bits at the output of the rxfifo are presented as the upper three bits of the status register included in each uart. the error status of a character, as reported by a read of the sr (status register upper three bits) can be provided in two ways, as programmed by the error mode control bit in the mode register: ocharacter mode o or the oblock modeo. the block mode may be further modified (via a cr command) to set the status bits as the characters enter the fifo or as they are read from the fifo. in the 'character' mode, status is provided on a character by character basis as the characters are read from the rxfifo: the ostatuso applies only to the character at the output of the rxfifo the next character to be read. in the 'block' mode (on entry) the status provided in the sr for these three bits is the logical or of the status for all characters coming to the input of the rxfifo since the last reset error command was issued. in this mode each of the status bits stored in the rxfifo are passed through a latch as they are sequentially written to the receiver fifo. if any of the characters has an error bit set that latch will set and remain set until it is reset with a areceiver reseto issued from the command register or a chip reset is issued. the purpose of this mode is indicating an error in the data block as opposed to an error in a character. this mode improves receiver service efficiency. in modern systems with low error rates, it is more efficient to ask for retransmit of a block error data than to analyze it on a byte by byte system. the above paragraph describes the block mode activity as the data is entered to the rxfifo. normally the status would be read only once at the beginning of the service to the receiver interrupt. if an error is not set then the entire amount of data in the rxfifo would be read without any more reading if the receiver status. this effectively doubles the efficiency of reading the receiver rxfifo. the use of the block mode on exit passes the data and error conditions as the rxfifo is read. here the final read of the status register would be after the last byte was read from the rxfifo. this delays the knowledge of an error condition until after the data has been read. the latch used in the block mode to indicate oproblem datao is usually set as the characters are read out of the rxfifo. via a command in the cr the latch may be configured to set as error characters are loaded to the rxfifo. this gives the advantage of indicating oproblem datao up to 256 (or the fifo size) characters earlier. in either mode, reading the sr does not affect the rxfifo. the rxfifo address is advanced only when the rxfifo is read. therefore, the sr should be read prior to reading the corresponding data character.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 13 if the rxfifo is full when a new character is received, the character is held in the receiver shift register until a position is available in the rxfifo. at this time there are 257 valid characters in the rxfifo. if an additional character is received while this state exists, the contents of the rxfifo are not affected: the character previously in the shift register is lost and the overrun error status bit, sr [4], will be set upon receipt of the start bit of the new (overrunning) character. wake up mode (also the a9bito, amultidropo, aparty; lineo or special mode) the sc28l202 provides four modes of this common asynchronous oparty lineo protocol where the parity bit is used to indicate that a byte is address data or information data. three automatic modes and the default host operated mode are provided. the automatic mode has several sub modes (see below). in the full automatic the internal state machine devoted to this function will handle all operations associated with address recognition, data handling, receiver enables and disables. in both modes the meaning of the parity bit is changed. it is often referred to as the a/d bit or the address/data bit sometimes the a9tho bit. it is used to indicate whether the byte presently in the receiver shift register is an oaddresso byte or a odatao byte. a o1o usually means address, a o0o data. its purpose is to allow several receivers connected to the same data source to be individually addressed. of course addressing could be by group also. normally the omastero would send an address byte to all receivers olisteningo. the remote receiver will be alookingo at the data stream for its address. upon recognition of its address it will enable itself to receive the following data stream. upon receipt of an address not its own it would then disable itself. as descried below appropriate status bits are available to describe the operation. again, for this mode an aaddress byteo is a byte that has the bit in the parity position set to logical 1. the use of the multidrop mode usually implies a amaster and slaveo configuration of the several uart stations so programmed. the software control should allow time for the slave stations to respond to the receipt of an address bit. often a reply from the addressed station is expected to confirm the receipt of the address. please see control the automatic features of the address recognition in mr0(1:0). enabling the wake up mode (this mode is variously referred to as a9bito or amultidropo.) this mode is selected by programming bits mr1 [4:3] (the parity bits) to '11'. the wake up feature has four modes of operation: one strictly under processor control and three automatic. these modes are controlled by bits 6, 1, 0 in the mr3 register. bit 6 controls the loading of the address byte to the rxfifo and mr0 [1:0] determines the sub mode as shown in the following list. mr3 [1:0] = 00 normal wake up mode (default) which is the same as previous duarts and is therefore controlled by the processor. the host controls operation via interrupts it receives and commands it writes to the duart command registers (cr). normal wake up (the default configuration) the enabling of the wakeup mode executes a partial enabling of the receiver state machine. even though the receiver has been reset the wake up mode will over ride the disable and reset condition. in the default (mode a00o above and the least efficient) configuration for this mode of operation, a 'master' station transmits an address character followed by data characters for the addressed 'slave' station. the slave stations, whose receivers are normally disabled (not reset), examine the received data stream. upon recognition of its address bit (this is the parity bit redefined to indicate the associated byte is an address bye not the address itself) interrupts the cpu (by setting rxrdy). the cpu (host) compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. upon receipt of another address character, the cpu may disable the receiver to initiate the process again. a transmitted character consists of a start bit; the programmed number of data bits, an address/data (a/d) bit and the programmed number of stop bits. the cpu selects the polarity of the transmitted a/d bit by programming bit mr1 [2]. mr1 [2] = 0 transmits a zero in the a/d bit position which identifies the corresponding data bits as data . mr1 [2] = 1 transmits a one in the a/d bit position which identifies the corresponding data bits as an address . the cpu should program the mode register prior to loading the corresponding data bytes into the txfifo. while in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. if disabled, it sets the rxrdy status bit and loads the character into the rxfifo if the received a/d bit is a one, but discards the received character if the received a/d bit is a zero. if the receiver is enabled, all received characters are transferred to the cpu via the rxfifo. in either case when the address character is recognized the data bits are loaded into the data fifo while the a/d bit is loaded into the status fifo position normally used for parity error (sr [5]). framing error, overrun error, and break detect operate normally whether or not the receiver is enabled. when the automatic modes are in operation the loading of the address character to the fifo is controlled by the mr0 (6) bit. the several automatic controls. these modes are concerned with the recognition of the address character itself ? mr3 [1:0] = 01 auto wake. enable receiver on address recognition for this station. upon recognition of its assigned address the local receiver will be enabled by the character recognition state machine and normal receiver communications with the host will be established. ? mr3 [1:0] = 10 auto doze. disable receiver on address recognition, not for this station. upon recognition of an address character that is not its own, in the auto doze mode, the receiver will be disabled by the character recognition state machine and the address just received either discarded or loaded to the rxfifo depending on the programming of mr0 [6]. ? mr3 [1:0] = 11 auto wake and doze. both modes described above. the programming of mr3 [1:0] to 11 will enable both the auto wake and auto doze features. the enabling of the wakeup mode executes a partial enabling of the receiver state machine. even though the receiver has been reset the wake up mode will over ride the disable and reset conditions. receiver reset and disable receiver disable stops the receiver immediately data being assembled in the receiver shift register is lost. data and status in the fifo is preserved and may be read. a reenable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. receiver reset will discard the present shift register data, reset the receiver ready bit (rxrdy), clear the status of the byte at the top of
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 14 the fifo and realign the fifo read/write pointers. this effectively aclearso the receiver fifo although the fifo data is not altered. receiver watchdog timer a `watchdog timer' is associated with each receiver. its interrupt is enabled by the awatchdogo bits of the awatch dog, character address, and x enableo register (wcxer). the purpose of this timer is to alert the control processor that characters are in the rxfifo which have not been read and/or the data stream has stopped. this situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. this counter times out after 64 bit times. it is reset each time a read of the rxfifo is executed. receiver timeout mode in addition to the watch dog timer described in the receiver section, the counter/timer may be used for a similar function. its programmability, of course, allows much greater precision of timeout intervals. the timeout mode uses the received data stream to control the counter. each time a received character is transferred from the shift register to the rxfifo, the counter is restarted. if a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. this mode can be used to indicate when data has been left in the rxfifo for more than the programmed time limit. otherwise, if the receiver has been programmed to interrupt the cpu when the receive fifo is full, and the message ends before the fifo is full, the cpu may not know there is data left in the fifo. the ctpu and ctpl value would be programmed for just over one character time, so that the cpu would be interrupted as soon as it has stopped receiving continuous data. this mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. in this case, the cpu has read all of the characters from the fifo, but the last character received has started the count. if there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. writing the appropriate command to the command register enables the timeout mode. writing an `ax' to cr a or cr b will invoke the timeout mode for that channel. writing a 0xcx to cr a or cr b will disable the timeout mode. ctpu and ctpl should be loaded with a countdown value that, with the selected clock, will generate a time period greater than the normal receive character period. the timeout mode disables the regular start/stop counter commands and puts the c/t into counter mode under the control of the received data stream. each time a received character is transferred from the shift register to the rxfifo, the c/t is stopped after 1 c/t clock, reloaded with the value in ctpu and ctpl and then restarted on the next c/t clock. if the c/t is allowed to end the count before a new character has been received, the counter ready bit, isr [3], will be set. if imr [3] is set, interrupt arbitration for the c/t will begin. invoking the `set timeout mode on' command, crx = `ax', clears the counter ready bit and stop the counter until the next character is received. exiting the time mode will clear the counter ready bit. arbitrating interrupt structure ( note : the advantages and intelligence of this system may be completely defeated by merely setting the arbitration value in the icr to 0x00 and not using the cir. one would then rely on traditional interrupt service by searching and testing various status registers on the assertion of the irqn.) the interrupt system determines when an interrupt should be asserted thorough an arbitration (or bidding) system. this arbitration is exercised over the several systems within the duart that may generate an interrupt. these will be referred to as ointerrupt sourceso. there are 18 in all and may of those have several sublevels. in general the arbitration is based on the fill level of the receiver fifo or the empty level of the transmitter fifo. the fifo levels are encoded into an 8bit number, which is concatenated to the channel number and source identification code. all of this is compared (via the bidding or arbitration process) to a user defined othresholdo. whenever a source exceeds the numerical value of the threshold the interrupt will be generated. interrupt sources that do not have a fifo are each provided with a aprogrammable fieldo that will determine their importance in the arbitration and type identification process. (see table 1 below) at the time of interrupt acknowledge (iackn) the source which has the highest bid (not necessarily the source that caused the interrupt to be generated) will be captured in a ocurrent interrupt registero (cir). this register will contain the complete definition of the interrupting source: channel, types of interrupt (receiver, transmitter, change of state, etc.) and fifo fill level. the value of the bits in the cir are used to drive the interrupt vector and global registers such that controlling processor may be steered directly to the proper service routine. a single read operation to the cir provides all the information needed to qualify and quantify the most common interrupt sources. the interrupt sources for each channel are listed below. ? transmit fifo empty level for each channel ? receive fifo fill level for each channel ? receiver with error for each channel ? change in break received status per channel ? change of state on channel input pins ? receiver watchdog time out event ? xon/xoff character recognition ? address character recognition ? countertimer ? no interrupt active (very useful in polled service and as a test value to terminate interrupt service) associated with the interrupt system are the interrupt mask register (imr) and the interrupt status register (isr) resident in each uart. programming of the imr selects which of the above sources may enter the arbitration process. the imr enables the interrupt. only the bidders in the isr whose associated bit in the imr is set to one (1) will be permitted to enter the arbitration process. the isr can be read by the host cpu to determine all currently active interrupting conditions. for convenience of reading the isr the mr1 (6) bit, when set, allows the reading of the isr masked by the bits of the imr. enabling and activating interrupt sources an interrupt source becomes enabled when writing a one to the proper interrupt mask register bit (imr) activates its interrupt capability. an interrupt source can never generate an irqn or have its obido or interrupt number appear in the cir unless the source has been enabled by the appropriate bit in an imr. an interrupt source is active if it is presenting its bid to the interrupt arbiter for evaluation. most sources have simple activation requirements. the watchdog timer, break received, xon/xoff or
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 15 address recognition and change of state interrupts become active when the associated events occur and the arbitration value generated thereby exceeds the threshold value programmed in the icr (interrupt control register). the transmitter and receiver functions have additional controls to modify the condition upon which the initiation of interrupt obiddingo begins: the txint and rxint fields of the mr0 and mr2 registers. these fields can be used to start bidding or arbitration when the rxfifo is not empty, 50% full, 75% full or 100% full. for the transmitter it is not full, 50% empty, 75% empty and empty. example: to increase the probability of transferring the contents of a nearly full rxfifo, do not allow it to start bidding until 50% or 75% full. this will prevent its relatively high priority from winning the arbitration process at low fill levels. a high threshold level could accomplish the same thing, but may also mask out low priority interrupt sources that must be serviced. note that for fast channels and/or long interrupt latency times using this feature should be used with caution since it reduces the time the host cpu has to respond to the interrupt request before receiver overrun occurs. setting interrupt priorities the bid or interrupt number presented to the interrupt arbiter is composed of character counts, channel codes, fixed and programmable bit fields. the interrupt values are generated for various interrupt sources as shown in table 1. the value represented by the bits 11 to 4 in table 1 are compared against the value represented by the athreshold. the athresholdo, bits 10 to 0 of the icr (interrupt control register), is aligned such that bit 0 of the threshold is compared to bit 1 of the interrupt value generated by any of the sources. whenever the value of the interrupt source is greater than the threshold the interrupt will be generated. the channel number arbitrates only against other channels. the threshold is not used for the channel arbitration. this results in channel b having the highest arbitration number. the decreasing order is b to a. if all other parts of an arbitration cycle are equal then the channel number will determine which channel will dominate in the arbitration process. note several characteristics of table 1 in bits 4:1. these bits contain the identification of the bidding source as indicated below: ? 0000 no interrupt source active ? x001 receiver without error ? x101 receiver with error (errors are: parity, framing and ? overrun. break is not considered an error ? x010 transmitter ? 1110 change of break ? 0110 change of state on i/o ports ? 0111 xon/xoff event ? 1011 address recognition ? x100 receiver watch dog ? 1000 counter timer ? 1111 rx loop back error the codes form bits 4:1 drive part of the interrupt vector modification and the global interrupt type register. the codes are unique to each source type and identify them completely. the channel numbering progresses from oao to obo as the binary numbers 0 to 1 and identify the interrupting channel uniquely. as the channels arbitrate obo will have the highest bidding value and oao the lowest table 1. interrupt values type bit 11:4 bit 3 bit 2 bit 1 bit 0 receiver w/o error rxfifo filled byte count 0 0 1 channel no. receiver w/ error rxfifo filled byte count 1 0 1 channel no. receiver watchdog rxfifo filled byte count 1 0 0 channel no. transmitter txfifo empty byte count 0 1 0 channel no. change of break programmed field 1 1 1 0 channel no. rx loop back error programmed field 1 1 1 1 channel no. change of state programmed field 0 1 1 0 port 0 or 1 xon/xoff programmed field 0 1 1 1 channel no. counter timer programmed field 1 0 0 0 counter 0 or 1 address recognition programmed field 1 0 1 1 channel no. no interrupt 0 0 0 0 0 threshold bits 7:0 of interrupt control register (icr) 0 0 0 0 0
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 16 interrupt arbitration and irqn generation interrupt arbitration is the process used to determine that an interrupt request should be presented to the host. the arbitration is carried out between the ointerrupt thresholdo and the osourceso whose interrupt bidding is enabled by the imr. the interrupt threshold is part of the icr (interrupt control register) and is a value programmed by the user. the osourceso present a value to the interrupt arbiter. that value is derived from four fields: the channel number, type of interrupts source, fifo fill level, and a programmable value. the interrupt request (irqn) will be asserted only when one or more of these values exceeds the threshold value in the interrupt control register will. following assertion of the irqn the host will either assert iackn (interrupt acknowledge) or will use the command to oupdate the ciro. at the time either action is taken the cir will capture the value of the source that is prevailing in the arbitration process. (call this value the winning bid). the sclk drives the arbitration process. it evaluates the 12 bits of the arbitration bus at the sclk rate developing a value for the cir every two sclk cycles. new arbitration values presented to the arbitration block during an arbitration cycle will be evaluated in the next arbitration cycle. for sources other than receiver and transmitters the user may set the high order bits of an interrupt source's bid value, thus tailoring the relative priority of the interrupt sources. the fill level of their respective fifos controls the priority of the receivers and transmitters. the more filled spaces in the rxfifo the higher the bid value; the more empty spaces in the txfifo the higher its priority. channels whose programmable high order bits are set will be given interrupt priority higher than those with zeros in their high order bits, thus allowing increased flexibility. the transmitter and receiver bid values contain the character counts of the associated fifos as high order bits in the bid value. thus, as a receiver's rxfifo fills, it bids with a progressively higher priority for interrupt service. similarly, as empty space in a transmitter's txfifo increases, its interrupt arbitration priority increases. the programmable fields allow the software to adjust the authority or value of the bid for those devices not having a fifo. for example: the break condition is sometimes used to signal a starting point in a continuous stream of data. a continuous running weather report or stock market atickertapeo report needs breaks in the data so that a receiver knows where the data starts. once start of the break is detected it is important to reset the achange of break a interrupt so that this bit can signal the condition of the break ending. this is signaled by the `l202 the setting another change of break event in the isr. since it is assumed the data will be starting very soon after the end of break it is important to give the change of break condition a high priority. this may be accomplished by setting the arbitration value for the achange of breako to a high value. the value in the achange of break programmable fieldo in table 1 would be 0x7f. iackn cycle, update cir when the host cpu responds to the interrupt, it will usually assert the iackn signal low. this will cause the duart to generate an iackn cycle in which the condition of the interrupting device is determined. when iackn asserts, the last valid interrupt number is captured in the cir. the value captured presents most of the important details of the highest priority interrupt at the moment the iackn (or the oupdate ciro command) was asserted. the dual uart will respond to the iackn cycle with an interrupt vector. the interrupt vector may be a fixed value, the content of the interrupt vector register, or when ointerrupt vector modificationo is enabled via icr, it may contain codes for the interrupt type and/or interrupting channel. this allows the interrupt vector to steer the interrupt service directly to the proper service routine. the interrupt value captured in the cir remains until another iackn cycle occurs or until an oupdate ciro command is given to the duart. the interrupting channel and interrupt type fields of the cir set the current ointerrupt contexto of the duart. the channel component of the interrupt context allows the use of global interrupt information registers that appear at fixed positions in the register address map. for example, a read of the global rxfifo will read the channel b rxfifo if the cir interrupt context is channel b receiver. at another time read of the grxfifo may read the channel a rxfifo (cir holds a channel a receiver interrupt) and so on. global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from fifos without explicitly addressing them. the cir will load with x'00 if iackn or update cir is asserted when the arbitration circuit is not asserting an interrupt. in this condition there is no arbitration value that exceeds the threshold value. when interrupt vector modification is active in this situation the interrupt vector bits associated with the cir will all be zero. global registers the oglobal registerso, 10 in all, are driven by the interrupt system. they are defined by the content of the cir (current interrupt register) as a result of an interrupt arbitration. in other words they are indirect registers pointed to by the content of the cir. the list of global register follows: ? gibcr the byte count of the interrupting fifo ? gicr channel number of the interrupting channel ? gitr type identification of interrupting channel ? grxfifo pointer to the interrupting receiver fifo ? gtxfifo pointer to the interrupting transmitter fifo a read of the grxfifo will give the content of the rxfifo that presently has the highest bid value. the purpose of this system is to enhance the efficiency of the interrupt system. the global registers and the cir update procedure are further described in the interrupt arbitration system polling, (normal and using the cir) many users prefer polled to interrupt driven service where there are not a large number of fast data channels and/or the host cpu's other interrupt overhead is low. the dual uart is functional in this environment. the most efficient method of polling is the use of the oupdate ciro command (with the interrupt threshold set to zero) followed by a read of the cir. this dummy write cycle will perform the same cir capture function that an iackn falling edge would accomplish in an interrupt driven system. a subsequent read of the cir, at the same address, will give information about an interrupt, if any. if the cir type field contains 0s, no interrupt is awaiting service. if the value is nonzero, the fields of the cir may be decoded for type; channel and character count information. optionally, the global interrupt registers may be read for particular information about the interrupt status or use of the global rxd and txd registers for data transfer as appropriate. the interrupt context will remain in the cir until another update cir command or an iackn cycle is initiated by the host cpu occurs. the cir loads with x'00 if update cir is asserted when the arbitration circuit has not detected an arbitration value that exceeds the threshold value of the icr. the global registers and cir may be used as avectorso to the service type required.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 17 traditional methods of polling status registers may also be used. their lower efficiency may be greatly offset by use of the ucir command and the read of the cir. they reduce the many reads and tests of status registers to only one read and one write. this would normally be accomplished by setting the interrupt threshold to zero. then the moment any system within the duart needs service the next poll of the cir would return a non zero value and the type field will inform the processor which of the possible 18 systems needs service. in the case of the fifos the number of bytes to be written or read is also available. character and address recognition (also used for multidrop, xon/xoff systems) character recognition is specific to each of the two uarts. three programmable characters are provided for the character recognition for each channel. the three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to omultidropo address recognition or inband xon/xoff flow control. character recognition system continually examines the incoming data stream. upon the recognition of a character bits appropriate for the character recognized are set in the xon/xoff interrupt status register (xisr) and in the interrupt status register (isr). the setting of these bit(s) will initiate any of the automatic sequences or and/or an interrupt that may have enabled via the mr0 register. note: reading the xisr clears the status bits associated with the recognition. the characters of the recognition system are fully programmable. the xon/xoff characters will be set to the standard characters if the hardware or software reset is used. the character recognition circuits are basically designed to provide generalpurpose character recognition. additional control logic has been added to allow for xon/xoff flow control and for recognition of the address character in the multidrop or owakeupo mode. this logic also allows for the generation of interrupts in either the generalpurpose recognition mode or the specific conditions mentioned above. the generality of the above provides a modicum of compatibility to bop (bit oriented protocol) where the generation and detection of aflagso is required. parts of usually synchronous bop protocols (hdlc in particular) are beginning to show up in asynchronous formats. character stripping the mr0 register provides for stripping the characters used for character recognition. recall that the character recognition may be conditioned to control several aspects of the communication. however this system is first a character recognition system. the status of the various states of this system is reported in the xisr and isr registers. the character stripping of this system allows for the removal of the specified control characters from the data stream: two for the xon /xoff and one for the wake up. via control in the mr0 register these characters may be discarded (stripped) from the data stream when the recognition system aseeso them or they may be sent on the rxfifo. whether they are stripped or not the recognition system will process them according to the action requested; flow control, wake up, interrupt generation, etc. care should be exercised in programming the stripping option if noisy environments are encountered. if a normal character were corrupted to a xoff character the transmitter would be stopped. if that character were now stripped from the fifo stack, then that stripping action would make it difficult to determine the cause of transmitter stopping. when character stripping is invoked and a recognition character is received that has an error bit set that character is sent to the rxfifo even though character stripping is active. flow control (xon/xoff) this section describes inband flow control or xon/xoff signaling. for the rts/cts hardware (outofband) control see mr1(7) and mr2(4) descriptions. the flow control is accomplished via the character recognition system giving recognition information to the flow control processor. xon and xoff are special characters used by a receiver to start and stop the remote transmitter that is sending it data. as described below several modes of manual and automatic flow control are available by program control. the modes of control are described in mr3(3:2) ? 00 = host mode ? 01 = auto transmit ? 10 = auto receive ? 11 = auto receive and transmit mode control xon/xoff mode control is accomplished via the mr0. bits 3 and 2 reset to zero resulting in all xon/xoff processing being disabled. if mr0 [2] is set, xon/xoff characters received may gate the transmitter. if mr0 [3] is set, the transmitter will transmit xon and xoff when triggered by attainment of fixed fill levels in the channel rxfifo. the mr0 [7] bit also has a xon/xoff function control. if this bit is set, a received xon or xoff character is not loaded into the rxfifo. if cleared, the poweron and reset default, the received xon or xoff character is loaded onto the rxfifo for examination by the host cpu. the mr0 (7) function operates regardless of the value in mr0 (3:2) xon xoff characters the programming of these characters is usually done individually. the standard xon/xoff characters are . xon is 0x11, xoff 0x13. any enabling of the xon/xoff functions will use the contents of the xon and xoff character registers as the basis on which recognition is predicated. host mode when neither the autoreceiver or autotransmitter modes are set, the xon/xoff logic is operating in the host mode. in host mode, all activity of the xon/xoff logic is initiated by commands to the crx. the xoff command forces the transmitter to disable exactly as though a xoff character had been received by the rxfifo. the transmitter will remain disabled until the chip is reset or the cr (7:3) = 10110 (xoff resume) command is given. in particular, reception of a xon or disabling or reenabling the transmitter will not cause resumption of transmission. redundant crtx commands, i.e. crtxon, crtxon, are harmless, although they waste time. a crtxon may be used to cancel a crtxoff (and vice versa) but both may be transmitted depending on the command timing with respect to that of the transmitter state machine. autotransmitter mode when a channel receiver loads a xoff character into the rxfifo, the channel transmitter will finish transmission of the current character and then stop transmitting. a transmitter so idled can be restarted by the receipt of a xon character by the receiver or by a hardware or
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 18 software reset. the last option results in the loss of the untransmitted contents of the txfifo. when operating in this mode the command register commands for the transmitter are not effective. while idle data may be written to the txfifo and it continue to present its fill level to the interrupt arbiter and maintains the integrity of its status registers. use of '00' as a xon/xoff character is complicated by the receiver break operation which loads a '00' character on the rxfifo. the xon/xoff character detectors do not discriminate in this case from a xon/xoff character received through the rxd pin. note : to be recognized as a xon or xoff character, the receiver must have room in the rxfifo to accommodate the character. an xon/xoff character that is received resulting in a receiver overrun does not effect the transmitter nor is it loaded into the rxfifo, regardless of the state of the xon/xoff transparency bit, mr0 (7). receiver mode since the receiving fifo resources in the dual uart are limited, some means of controlling a remote transmitter is desirable in order to lessen the probability of receiver overrun. the dual uart provides two methods of controlling the data flow. there is a hardwareassisted means of accomplishing control, the socalled outofband flow control, and an inband flow control method. the outofband flow control is implemented through the ctsnrtsn signaling via the i/o ports. the operation of these hardware handshake signals is described in the receiver and transmitter discussions. inband flow control is a protocol for controlling a remote transmitter by embedding special characters within the message stream, itself. two characters, xon and xoff, which do not represent normal printable character take on flow control definitions when the xon/xoff capability is enabled. flow control characters received may be used to gate the channel transmitter on and off. this activity is referred to as autotransmitter mode. to protect the channel receiver from overrun, fixed fill levels (hardware set at 240 characters) of the rxfifo may be employed to automatically insert xon/xoff characters in the transmitter's data stream. this mode of operation is referred to as autoreceiver mode. commands issued by the host cpu via the cr can simulate all these conditions. auto receive and transmit this is a combination of both modes. note: xon /xoff characters the xon/xoff character with errors will be accepted as valid. the user has the option sending or not sending these characters to the fifo. error bits associated with xon/xoff will be stored normally to the receiver fifo. the channel's transmitter may be programmed to automatically transmit a xoff character without host cpu intervention when the rxfifo fill level exceeds a fixed limit (240). in this mode it will transmit a xon character when the rxfifo level drops below a second fixed limit (16). a character from the txfifo that has been loaded into the txd shift register will continue to transmit. character(s) in the txfifo that have not been loaded to the transmitter shift register are unaffected by the xon or xoff transmission. they will be transmitted after the xon/xoff activity concludes. if the fill level condition that initiates xon activity negates before the flow control character can begin transmission, the transmission of the flow control character will not occur. that is, either of the following sequences may be transmitted depending on the timing of the fifo level changes with respect to the normal character times: fix this character xoff xon character character character hardware keeps track of xoff characters sent that are not rescinded by a xon. this logic is reset by writing mr0 (3) to '0'. if the user drops out of autoreceiver mode while the xisr shows xoff as the last character sent the xon/xoff logic would not automatically send the negating xon. the kill crtx command (of the command register) can be used to cleanly terminate any pending crtx commands. note : in no case will a xon/xoff character transmission be aborted. once the character is loaded into the tx shift register, transmission continues until completion or a chip reset or transmitter reset is encountered. the kill crtx command has no effect in either of the auto modes. xon/xoff interrupts the xon/xoff logic generates interrupts only in response to recognizing either of the characters in the xoncr or xoffcr (xon or xoff character registers). the transmitter activity initiated by the xon/xoff logic or any cr command does not generate an interrupt. the character comparators operate regardless of the value in mr0 (3:2). hence the comparators may be used as generalpurpose character detectors by setting mr0 (3:2)='00' and enabling the xon/xoff interrupt in the imr. the dual uart can present the xon/xoff recognition event to the interrupt arbiter for irqn generation. the irqn generation may be masked by setting bit 4 of the interrupt mask register, imr. the bid level of a xon/xoff recognition event is controlled by the bidding control register x, bcrx, of the channel. the interrupt status can be examined in isr [4]. if cleared, no xon/xoff recognition event is interrupting. if set, a xon or xoff recognition event has been detected. the x interrupt status register, xisr, can be read for details of the interrupt and to examine other, noninterrupting, status of the xon/xoff logic. refer to the xisr in the register descriptions. the character recognition function and the associated interrupt generation is disabled on hardware or software reset. multidrop or wake up or 9 bit mode this mode is used to address a particular uart among a group connected to the same serial data source. normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data. while this method is fully supported in the sc28l202 it also supports recognition of the character itself. upon recognition of its address the receiver will be enabled and data loaded onto the rxfifo. further the address recognition has the ability, if so programmed, to disable (not reset) the receiver when an address is seen that is not recognized as its own. the particular features of oauto wake and auto dozeo are described in the detail descriptions under areceiver operationo above. note : care should be taken in the programming of the character recognition registers. programming x'00, for example, may result in a break condition being recognized as a control character. this will be further complicated when binary data is being processed.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 19 programming the host interface writing control words into the appropriate registers programs the operation of the duart. operational feedback is provided via status registers that can be read by the cpu. the addressing of the registers is described in the register map. the contents of certain control registers are initialized to zero on reset. care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. for example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. in general, the contents of the mr, the csr, and the opcr should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the acr should only be made while the c/t is stopped. each channel has 3 mode registers (mr0, 1, 2) which control the basic configuration of the channel. mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. refer to table 2 for register bit descriptions.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 20 register description and programming note programmers may use either of two register sets or mix the features of each. it is suggested that only the extended register set be used in new designs. however if a system needed to use a block of communications code written for an older system then that code could merely be called. this is similar to calling a dos ? program in a windows ? environment. before calling legacy code it is recommended (but not required) to execute areset to c92o command. also consideration must be given to the i/o pins to avoid contention of drivers of the pins and an external driver. two control register descriptions and maps are implemented in the sc28l92: one represents the previous 4bit address and the other the new 7bit address space representing the all the new features of the new design. the design of the sc28l202 allows for high degree with former philips two channel communications controllers duarts. to facilitate this feature the complete register function and control of the sc26c92 is replicated in the sc28l202. that is code written for the scn2681, scn68681, scc2692, scc68692 and sc26c92 will operate with this device. with the execution of code written for previous duarts and immediately after a hardware reset or a areset to c92o command the following configuration will exist: 1. the size of all fifos is set to 8 bytes (for legacy code). 2. fifo interrupt levels are controlled by the bits of the mr registers 3. all i/o ports are set to input. 4. receiver fifo set to interrupt on fifo ready. 5. transmitter fifo set to interrupt on fifo empty. 6. baud selection follows previous 4 bit programming and baud rate grouping controlled by the mr and acr registers. table 2. sc28l202 register bit descriptions registers that control global properties of the 28l202 gccr global configuration control register this is a very important register! it should be the first register addressed during initialization. hex bit (7) bit (6) bit (5:3) bit(2:1) bit 0 addr reserved dackn assertion reserved ivc interrupt vector control isr read mode 0 slow (timed by 2 sclk edges) 1 fast (asynchronous) set to 0 00 = no interrupt vector 01 = ivr(7:0) 10 = ivr(7:1) + channel code 11 = ivr(7:5) + interrupt type + channel code 0 = isr unmasked 1 = isr read masked by imr gccr(7:6) dackn assertion motorola bus cycle time can be controlled by selecting a dackn assertion time based on x1/sclk speed . see examples below. x1/sclk #sclk cycles delay 3.6864 mhz 1/21 136272 ns 7.3728 mhz 1/21 68136 ns 14.7456 mhz 1/21 3468 ns 29.4912 mhz 12 3468 ns 33.1776 mhz 23 6090 ns 44.2368 mhz 23 4668 ns gccr(5:3): reserved gccr(2:1): interrupt vector configuration the ivc field controls if and how the assertion of iackn (the interrupt acknowledge pin) will form the interrupt vector for the duart. if b'00, no vector will be presented during an iackn cycle. the bus will be driven high (0xff). if the field contains a b'01, the contents of the ivr, interrupt vector register, will be presented as the interrupt vector without modification. if ivc = 0x10, the channel code will replace the lsb of the ivr; if ivc = b'11 then a modified interrupt type and channel code replace the 3 lsbs of the ivr. note : the modified type field ivr(2:1) is: ? 10 receiver w/o error ? 11 receiver with error ? 01 transmitter ? 00 all remaining sources gccr(0): interrupt status masking this bit controls the readout mode of the interrupt status register, isr. if set, the isr reads the current status masked by the imr, i.e. only interrupt sources enabled in the imr can ever show a '1' in the isr. if cleared, the isr shows the current status of the interrupt source without regard to the interrupt mask setting. sfsr a and b special feature & status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2:1 bit 0 reserved reserved reserved reserved loop back error remote loop error check reserved 0 = no 1 = yes (read only) 00 = disabled 01 = enabled, rxc ? txc 10 = enabled, rxc ? txcn
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 21 sfsr(7:4) reserved sfsr(3) status of loop back error check. a a1o indicates a loop back error occurred, which will be entered for interrupt arbitration. it can be cleared by the processor by a write to this register with d(3) equal to a1o. sfsr(2:1) certification of returned data as valid (this feature implies the transmitted data is being returned by the remote receiver. ) sets automatic checking of returned data. this mode stores transmitted data and compares it to data returned from the remote receiver. it is used where relative short delay times are available, up to two characters in time . this mode will totally relieve the processor of this task where certainty of transmission and reception is required. the transmitted data is looped back by the remote station with a halfbit time delay. the local transmitted data is internally sent to the local receiver for comparison. an interrupt is generated in the case of an error (data mismatch, parity or framing). 00 = the checking is disabled 01 = return data is clocked in on rise of txc 10 = return data is clocked on of rise of txcn 00 = reserved sfsr(0) reserved trr test and revision register. trr bit 7 bit 6:0 test 2 revision code trr(7) test 2 enable bypass divide by 16 counter in all txc and rxc. trr [6:0] chip revision code indicates the revision of the chip. initial code will be 0000000 . the revision code bits (6:0) are hard wired. the default setting of the test bits is all zero. stcr scan test control register. addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 77 memory test scan test iddq test stcr(0) iddq test turns off all pullup devices on the i/o pins. ses system enable status register, a and b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved transmitter enabled receiver enabled watch dog timer address recognition xon xoff set to 0 set to 0 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes this register reports the enabled status of the several sub systems in the duart. these systems are sometimes controlled by the state machines of the receiver fifos. eos enhanced operation status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved i/o port operation reserved counter/timer 0 clock select channel b rx/tx clock selection channel a rx/tx clock selection channel b fifo interrupt level control channel a fifo interrupt level control 0 = default 1 = enhanced 0 = default 1 = enhanced 0 = default 1 = enhanced 0 = default 1 = enhanced 0 = default 1 = enhanced 0 = default 1 = enhanced this register reports the status of the enhanced operation in several sub systems in the duart.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 22 uart registers these registers are generally concerned with formatting, transmitting and receiving data. the user must exercise caution when changing the mode of running receivers, transmitters, pbrg or counter/timers. the selected mode will be activated immediately upon selection, even if this occurs during the reception or transmission of a character. it is also possible to disrupt internal controllers by changing modes at critical times, thus rendering later transmission or reception faulty or impossible. an exception to this policy is switching from autoecho or remote loop back modes to normal mode. if the deselecting occurs just after the receiver has sampled the stop bit (in most cases indicated by the assertion of the channel's rxrdy bit) and the transmitter is enabled, the transmitter will remain in autoecho mode until the end of the transmission of the stop bit. mr0 mode register 0, a and b mr0 can be accessed directly at h'20o and h'28o in the extended section of the address map, or by means of the amr pointerso at the 0x00 and 0x08 address pointers used by legacy code. (test 1) (test 3) bit 7 bit 6 bit (5:4) bit 3 bit 2 bit 1 bit 0 mr0 a, mr0 b, and mr0 b[3:0] are reserved rx watchdog * 0 = disable 1 = enable rxint bit 2 see tables in mr0 description txint (1:0) see table 13 fifo size 0 = 8 bytes 1 = 256 bytes baud rate extended ii 0 = normal 1 = extend ii reserved set to 0 baud rate extended 1 0 = normal 1 = extend *this bit control is duplicated at mr0[7]. mr0[7] fixed length watchdog timer this bit controls the receiver watchdog timer. 0 = disable, 1 = enable. when enabled, the watch dog timer will generate a receiver interrupt if the receiver fifo has not been accessed within 64 bit times of the receiver 1x clock. this is used to alert the control processor that data is in the rxfifo that has not been read. this situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. mr0[6] bit 2 of receiver fifo interrupt level. this bit along with bit 6 of mr1 sets the fill level of the 8 byte fifo that generates the receiver interrupt. mr0[6] and mr1[6] note that this control is split between mr0 and mr1. this is for backward compatibility to the sc2692 and scn2681. table 3. receiver fifo interrupt fill level mr0(3)=0 mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rxrdy) 01 3 or more bytes in fifo 10 6 or more bytes in fifo 11 8 bytes in fifo (rx full) table 4. receiver fifo interrupt fill level mr0(3)=1 mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rxrdy) 01 128 or more bytes in fifo 10 192 or more bytes in fifo 11 256 bytes in fifo (rx full) for the receiver these bits control the number of fifo positions filled when the receiver will attempt to interrupt. after the reset the receiver fifo is empty. the default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it. mr0[5:4] tx interrupt fill level. table 5. transmitter fifo interrupt fill level mr0(3)=0 mr0[5:4] interrupt condition 00 8 bytes empty (tx empty) 01 4 or more bytes empty 10 6 or more bytes empty 11 1 or more bytes empty (txrdy) table 6. transmitter fifo interrupt fill level mr0(3)=0 mr0[5:4] interrupt condition 00 256 bytes empty (tx empty) 01 128 or more bytes empty 10 192 or more bytes empty 11 1 or more bytes empty (txrdy) for the transmitter these bits control the number of fifo positions empty when the receiver will attempt to interrupt. after the reset the transmit fifo has 8 bytes empty. it will then attempt to interrupt as soon as the transmitter is enabled. the default setting of the mr0 bits (00) condition the transmitter to attempt to interrupt only when it is completely empty. as soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request. mr0[3] fifo size selects between 8 or 256 byte fifo structure mr0[2:0] legacy baud rate group selection these bits are used to select one of the sixbaud rate groups. see table 13 for the group organization. ? 000 normal mode ? 001 extended mode i ? 100 extended mode ii other combinations of mr2[2:0] should not be used note: mr0[3:0] are not used in channel b and should be set to 0.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 23 mr1 mode register 1, a and b mr1 can be accessed directly at h'21o and h'29o in the extended section of the address map, or by means of the amr pointerso at the 0x00 and 0x08 address pointers used by legacy code. bit 7 bit 6 bit 5 bit 4:3 bit 2 bit 1:0 rxrts control see tables in mr0 description error mode parity mode parity type bits per character 0 = off 1 = on 0 = character 1 = block (entry or exit) 00 = with parity 01 = force parity 10 = no parity 11 = multi drop special mode 0 = even 1 = odd 00 = 5 01 = 6 10 = 7 11 = 8 mr1[7] receiver request to send (hardware flow control) this bit controls the deactivation of the rtsn output (i/o2) by the receiver. the i/o2 output is asserted and negated by commands applied via the command register or through the setting of the opr register bits. mr1[7] = 1 enables the receiver state machine to controls the sate of the i/o2 (where the rtsn function is assigned) to be automatically negated (driven high) upon receipt of a valid start bit if the receiver fifo is 240 full or greater. (for 8byte mode the fifo full signal is used) rtsn is reasserted when the fifo fill level falls below 240 filled fifo positions. this constitutes a change from previous members of philips (signets)' uart families where the rtsn function triggered on fifo full. this behavior caused problems with pc uarts that could not stop transmission at the proper time. note: when the fifo is set to an 8byte depth the rtsn signaling is triggered on position 8 of the fifo the rtsn feature can be used to prevent overrun in the receiver, by using the rtsn output signal, to control the ctsn (see mr2(4) description) input of the transmitting device. it is not recommend to use the hardware flow control and the ainbando (xon/xoff) flow control at the same time although the duart hardware will allow it. to use the rtsn function: 1. set mr1(7) to 1 2. set i/o0 b or i/o1 b as appropriate to logical 0 3. enable receiver mr1[6] receiver interrupt control bit 1. see description under mr0 [6]. (writing to this register will reset the rxfifo interrupt to the bit configuration of mr0 and mr1. reading has no effect.) *** change in mr in legacy section at mr0 also*** mr1 [5] error mode select and sub modes this bit selects the operating mode of the three fifoed status bits (fe, pe, and received break). in the character mode, status is provided on a character by character basis; the status applies only to the character at the output of the fifo. in the block mode, the status provided in the sr for these bits is the accumulation (logical or) of the status for all characters coming to the output of the fifo, since the last reset error command was issued. the block error mode has twosub mode. these modes are controlled by the command register. the error is aaccumulatedo (as described above) at either the entry of the data in to the fifo or on the exit (read of the fifo). of the two the setting of the error on the entry of the data into the fifo gives the earliest warning of error data. mr1[4:3] parity mode select if 'with parity' or 'force parity' is selected, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. mr1[4:3] = 11 selects the channel to operate in the special wake up mode. mr1[2] parity type select this bit sets the parity type (odd or even) if the 'with parity' mode is programmed by mr1[4:3], and the polarity of the forced parity bit if the 'force parity' mode is programmed it has no effect if the 'no parity' mode is programmed. in the special 'wake up' mode, it selects the polarity of the a/d bit. the parity bit is used to an address or data byte in the 'wake up' mode. mr1[1:0] bits per character select this field selects the number of data bits per character to be transmitted and received. this number does not include the start, parity, or stop bits.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 24 mr2 mode register 2, a and b mr2 can be accessed directly at 0x22 and 0x2a in the extended section of the address map, or by means of the amr pointerso at t he 0x00 and 0x08 address pointers used by legacy code. the mr2 register provides basic channel setup control that may need more frequent updating. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr2 a mr2 b channel mode tx controls rts cts enable tx stop bit length note: add 0.5 to binary codes 0 7 for 5 bit character lengths. 00 = normal 01 = autoecho 10 = local loop 11 = remote loop 0 = no 1 = yes 0 = no 1 = yes 0 = 0.563 4 = 0.813 8 = 1.563 c = 1.813 1 = 0.625 5 = 0.875 9 = 1.625 d = 1.875 2 = 0.688 6 = 0.938 a = 1.688 e = 1.938 3 = 0.750 7 = 1.000 b = 1.750 f = 2.000 note: 1. add 0.5 to values shown for 0 7 if channel is programmed for 5 bits/char. mr2[7:6] mode select the duart can operate in one of four modes: normal, automatic echo, local loop back and remote loop back mr2[7:6] = b'00 normal mode normal and default mode the transmitter and receiver operating independently. mr2[7:6] = b'01 automatic echo places the channel in the automatic echo mode, which automatically retransmits the received data. the following conditions are true while in automatic echo mode: ? received data is reclocked and retransmitted on the txd output. ? the receiver clock is used for the transmitted data. ? the receiver must be enabled, but the transmitter need not be enabled. ? the txrdy and tx idle status bits are inactive. ? the received parity is checked, but is not regenerated for transmission, i.e., transmitted parity bit is as received. ? character framing is checked, but the stop bits are retransmitted as received. rx data is sent to rxfifo ? a received break is echoed as received until the next valid start bit is detected. ? cpu to receiver communication continues normally, but the cpu to transmitter link is disabled. mr2[7:6] = b'10 selects local loop back diagnostic mode. in this mode: ? the transmitter output is internally connected to the receiver input. ? the transmitter's 1x clock is used for the receiver. ? the txd output is held high. ? the rxd input is ignored. ? the transmitter must be enabled, but the receiver need not be enabled. ? cpu to transmitter and receiver communications continue normally. mr2 [7:6] = b'11 selects the remote loop back diagnostic mode. in this mode: ? received data is reclocked and retransmitted on the txd output. ? the receiver 1x clock is used for the transmitted data. ? received data is not sent to the local cpu, and the error status conditions are inactive. ? the received parity is not checked and is not regenerated for transmission, i.e., the transmitted parity bit is as received. ? the receiver must be enabled, but the transmitter need not be enabled. ? character framing is not checked, and the stop bits are retransmitted as received. ? a received break is echoed as received until the next valid start bit is detected. mr2[5] transmitter request to send control this bit controls the deactivation of the rtsn output (i/o2) by the transmitter. this output is manually asserted and negated by appropriate commands issued via the command register. mr2 [5] = 1 negates (drives to logical 1) rtsn automatically one bit time after the characters in the transmit shift register and in the txfifo (if any) are completely transmitted (includes the programmed number of stop bits if the transmitter is not enabled). this feature can be used to automatically terminate the transmission of a message as follows: ? program auto reset mode: mr2[5]= 1. ? enable transmitter. ? assert rtsn via command. ? send message. ? verify the next to last character of the message is being sent by waiting until transmitter ready is asserted. disable transmitter after the last character is loaded into the txfifo. ? the last character will be transmitted and rtsn will be reset one bit time after the last stop bit. note: when the transmitter controls the rtsn pin the meaning of the pin is completely changed. it has nothing to do with the normal rtsn/ctsn ahandshakingo. it is usually used to mean, aend of messageo and to aturn the line aroundo in simplex communications. from a practical point of view the simultaneous use of tx control of rtsn and rx control is mutually exclusive. however if this is programmed the duart performs as required. mr2[4] clear to send control the state of this bit determines if the ctsn input (i/o0) controls the operation of the transmitter. if this bit is 0, ctsn has no effect on the transmitter. if this bit is a 1, the transmitter checks the state of ctsn each time it is ready to begin sending a character. if it is asserted (low), the character is transmitted. if it is negated (high), the txd output remains in the marking state and the transmission is delayed until ctsn goes low. changes in ctsn, while a character is being transmitted, do not affect the transmission of that character. this feature can be used to prevent overrun of a remote receiver. mr2[3:0] stop bit length select this field programs the length of the stop bit appended to the transmitted character. stop bit lengths of 9/16 through 2 bits can be programmed. in all cases, the receiver only checks for a mark condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled). if an external 1x clock is used for the transmitter, mr2[1] = 0 selects one stop bit and mr2[1] = 1 selects two stop bits to be transmitted.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 25 mr3 mode register 3, a and b bit 7 bit 6 bit 5:4 bit 3:2 bit 1:0 xon/xoff 1 transparency address recognition 1 transparency reserved inband flow control mode address recognition control 0 = flow control characters received are loaded onto the rxfifo 1 = flow control characters received are not loaded onto the rxfifo 0 = address characters received are loaded to rxfifo 1 = address characters received are not loaded onto the rxfifo 00 = host mode, only the host cpu may initiate flow control actions through the cr 01 = auto transmitter flow control 10 = auto receiver flow control 11 = auto rx and tx flow control 00 = default 01 = auto wake 10 = auto doze 11 = auto wake and auto doze note: 1. if these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0) mr3[7 & 6] xon/xoff character stripping control the handling of recognized xon/xoff or address characters. if set, the character codes are placed on the rxfifo along with their status bits just as ordinary characters are. if the character is not loaded onto the rxfifo, its received status will be lost unless the receiver is operating in the block error mode, see mr1[5] and the general discussion on receiver error handling. interrupt processing is not effected by the setting of these bits. see character recognition section. mr3[5:4] reserved mr3[3:2] xon/xoff processing control the xon/xoff processing logic. auto transmitter flow control allows the gating of transmitter activity by xon/xoff characters received by the channel's receiver. auto receiver flow control causes the transmitter to emit an xoff character when the rxfifo has loaded to a depth of 240 characters. draining the rxfifo to a level of 128 or less causes the transmitter to emit a xon character. all transmissions require no host involvement. a setting other than b'00 in this field precludes the use of the command register to transmit xon/xoff characters. note: interrupt generation in xon/xoff processing is controlled by the imr (interrupt mask register) of the individual channels. the interrupt may be cleared by a read of the xisr, the xon/xoff interrupt status register. receipt of a flow control character will always generate an interrupt if the imr is so programmed. the mr0[3:2] bits have effect on the automatic aspects of flow control only, not the interrupt generation. mr3[1:0] address recognition this field controls the operation of the address recognition logic. if the device is not operating in the special or owakeupo mode, this hardware may be used as a generalpurpose character detector by choosing any combination except b'00. interrupt generation is controlled by the channel imr. the interrupt may be cleared by a read of the xisr, the xon/xoff interrupt status register. see further description in the section on the wake up mode.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 26 rxcsr receiver clock select register a and b txcsr transmitter clock select register a and b both registers consist of single 6bit field that selects the clock source for the receiver and transmitter respectively. durin g a read the unused bits in this register read b'000. the abrgo baud rates (fixed brg rates) shown in the table below are based on the sclk crystal frequency of 14.7456 mhz. the baud rates shown below will vary as the sclk crystal clock varies. for example, if the sclk rate is changed to 7.3728 mhz all the rates below will reduce by 1/2. bit 7 bit 6 bits 5:0 reserved reserved transmitter/receiver clock select code, see clock multiplex table below rx and tx clock select table note : sclk maximum rate is 50 mhz. data clock rates will follow exactly the ratio of the x1/sclk to 14.7654 mhz tx a clock select code clock selection, sclk = 14.7456 mhz tx a clock select code clock selection, sclk = 14.7456 mhz 00 0000 brg 50 01 0000 brg 75 00 0001 brg 110 01 0001 brg 150 00 0010 brg 134.5 01 0010 brg 450 00 0011 brg 200 01 0011 brg 1800 00 0100 brg 300 01 0100 brg 2000 00 0101 brg 600 01 0101 brg 14.4k 00 0110 brg 1200 01 0110 brg 19.2k 00 0111 brg 1050 01 0111 brg 28.8k 00 1000 brg 2400 01 1000 brg 57.6k 00 1001 brg 4800 01 1001 brg 115.2k 00 1010 brg 7200 01 1010 brg 230.4k 00 1011 brg 9600 01 1011 brg 460.8k 00 1100 brg 38.4k 01 1100 brg 921.6k 00 1101 timer 0 01 1101 timer 1 00 1110 i/o3 a transmitter 16x external * 01 1110 pbrg 0 00 1111 i/o3 a transmitter 1x external * 01 1111 midi rate 31.25 khz 1.66% error tx a clock select code clock selection, sclk = 14.7456 mhz tx a clock select code clock selection, sclk = 14.7456 mhz 11 0000 to 11 1101 reserved 11 1110 pbrg 1 11 1111 reserved this field selects the baud rate clock for the channel a transmitter. * external clock pin and external clock mode assignment. tx/rx csr x [5:0] rxc channel a txc channel b rxc channel b 001110 i/o4 a 16x i/o5 a 16x i/o6 a 16x 001111 i/o4 a 1x i/o5 a 1x i/o6 a 1x
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 27 crx command register extension, a and b cr is used to write commands to the duart. bit 7 bit 6 bit 5 bit 4:0 lock tx and rx enables enable tx enable rx command register codes. 0 = lock rx & tx state 1 = change rx & tx state 0 = disable 1 = enable 0 = disable 1 = enable (see command register table) cr[7] lock tx and rx enables. if reset, the transmitter and receiver enable bits, cr[6:5] are not significant. the enabled/disabled state of a receiver or transmitter can be changed only if this bit is a a1o during the time of the write to the command register. writes to the lower 5 bits of the cr would usually have cr[7] at a0o to maintain the condition of the receiver and transmitter. the bit provides a mechanism for writing commands to a channel, via cr[4:0], without the necessity of keeping track of or reading the current enable status of the receiver and transmitter. cr[6] enable transmitter a one written to this bit enables operation of the transmitter. the txrdy status bit will be asserted. when disabled by writing a zero to this bit, the command terminates transmitter operation and resets the txrdy and tx idle status bits returning the transmitter to its idle state . however, if a character is being transmitted or if characters are loaded in the txfifo when the transmitter is disabled, the transmission of the all character(s) is completed before assuming the inactive state. cr[5] enable receiver a one written to this bit enables operation of the receiver. the receiver immediately begins the search for and the verification the start bit. if a zero is written, this command terminates operation of the receiver immediately a character being received will be lost. the command has no effect on the receiver status bits or any other control registers. the data in the rxfifo will be retained and may be read. if the receiver is reenabled subsequent data will be appended to that already in the rxfifo. if the special wakeup mode is programmed, the receiver operates even if it is disabled (see wakeup mode). cr[4:0] miscellaneous commands (see table below) the encoded value of this field can be used to specify a single command as follows: ? 00000 no command. ? 00001 reserved ? 00010 reset receiver. immediately resets the receiver as if hardware reset had been applied. the receiver is reset and the fifo pointer is reset to the first location effectively discarding all unread characters in the fifo. ? 00011 reset transmitter. immediately resets the transmitter as if a hardware reset had been applied. the transmitter is reset and the fifo pointer is reset to the first location effectively discarding all untransmitted characters in the fifo. ? 00100 reset error status. clears the received break, parity error, framing error, and overrun error bits in the status register (sr[7:4]). it is used in either character or block mode. in block mode it would normally be used after the block is read. ? 00101 reset break change interrupt. causes the break detect change bit in the interrupt status register (isr[2]) to be cleared to zero. ? 00110 start break. forces the txd output low (spacing). if the transmitter is empty, the start of the break condition will be delayed up to two bit times. if the transmitter is active and the txfifo is empty then the break begins when transmission of the current character is completed. if there are characters in the txfifo, the start of break is delayed until all characters presently in the txfifo and any subsequent characters loaded have been transmitted. (tx idle must be true before break begins). the transmitter must be enabled to start a break. ? 00111 stop break. the txd line will go high (marking) within two bit times. txd will remain high for one bit time before the next character is transmitted. ? 01000 assert rtsn. causes the rtsn output to be asserted (low). ? 01001 negate rtsn. causes the rtsn output to be negated (high). note : the two commands above actually reset and set, respectively, the i/o0 b (channel a) or i/o1 b (channel b) pin associated with the opr register. (see sopr and ropr registers i/o pin control. ? 01010 set c/t receiver time out mode on ? 01011 set mr pointer to 0 ? 01100 set c/t receiver time out mode off ? 01101 block error status accumulation on fifo entry. allows the areceived breako, aframing erroro and aparity erroro bits to be set as the received character is loaded to the rxfifo. (normally these bits are set on reading of the data from the rxfifo) setting this mode can give information about error data up to 256 bytes earlier than the normal mode. however it clouds the ability to know precisely which byte(s) are in error. ? 01110 power down mode on ? 01111 disable power down mode ? 10000 transmit an xon character ? 10001 transmit an xoff character ? 10010 c/t start sets the counter timer to the value of the counter/timer preset register and starts the counter. ? 10011 c/t stop effectively stops the counter/timer, captures the last count value and resets the counter ready status bit in the isr ? 10100 reserved ? 10101 reserved. ? 10110 transmitter resume command (this command is not active in aautotransmit modeo). a command to cancel a previous host xoff command. upon receipt, the channel's transmitter will transfer a character, if any, from the txfifo and begin transmission.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 28 ? 10111 host xoff (or transmitter pause) command (crtxoff). this command allows tight host cpu control of the flow control of the channel transmitter. when interrupted for receipt of a xoff character by the receiver, the host may stop transmission of further characters by the channel transmitter by issuing the host xoff command. any character that has been transferred to the txd shift register will complete its transmission, including the stop bit before the transmitter pauses. even though the transmitter is paused it is still able to send xon/xoff by the request of its associated receiver. ? 11000 cancel host transmit flow control command. issuing this command will cancel a previous command to transmit a flow control character if the flow control character is not yet loaded into the txd shift register. if there is no character waiting for transmission or if its transmission has already begun, then this command has no effect and the character will be sent. ? 11001 reserved ? 11010 reserved ? 11011 reset address recognition status. this command clears the interrupt status that was set when an address character was recognized by a disabled receiver operating in the special mode. ? 11100 reserved ? 11101 block error status accumulates on fifo read (default state) ? 11110 reset to ac92o register set ? 11111 reserved for channel b, for channel a: executes a chip wide reset. executing this command in channel a is equivalent to a hardware reset with the reset(n) pin. executing in channel b has no effect. command register extension table a and b commands 0x0f, 0x0f, 0xff (marked with * ) are global and exist only in channel a's register space. channel command code channel command channel command code channel command cr[4:0] description cr[4:0] description 0 0000 nop 1 0000 transmit xon 0 0001 set mr pointer to 1 1 0001 transmit xoff 0 0010 reset receiver 1 0010 start c/t 0 0011 reset transmitter 1 0011 stop c/t 0 0100 reset error status 1 0100 reserved 0 0101 reset break change interrupt 1 0101 reserved 0 0110 begin transmit break 1 0110 transmitter resume command (crxoffre) 0 0111 end transmit break 1 0111 host xoff command (crtxoff) 0 1000 assert rtsn (i/o0 b or i/o1 b) 1 1000 cancel transmit x char command (crtx) 0 1001 negate rtsn (i/o0 b or i/o1 b) 1 1001 reserved 0 1010 set c/t receiver timeout mode on 1 1010 reserved 0 1011 set mr pointer to 0 1 1011 reset address recognition status 0 1100 set c/t receiver timeout mode off 1 1100 reserved 0 1101 block error status on rxfifo load 1 1101 block error status on rxfifo read 0 1110 ? power down mode on 1 1110 reserved 0 1111 ? disable power down mode 1 1111 ? reset device as a hardware reset. reserved in channel b*
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 29 sr channel status register a and b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received break framing error parity error overrun error tx idle txrdy rxfull rxrdy 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes sr[7] received break this bit indicates that an all zero character (including parity, if used) of the programmed length has been received with a stop bit at a logical zero. a single fifo position is loaded with 0x00 when a break is received; further entries to the fifo are inhibited until the rxd line returns to the marking state for at least one half bit time (two successive edges of the internal or external 1x clock). when this bit is set, the change in break bit in the isr (isr [2]) is set. isr[2] is also set when the end of the break condition, as defined above, is detected. the break detect circuitry is capable of detecting breaks that originate in the middle of a received character. however, if a break begins in the middle of a character, it must last until the end of the next character in order for it to be detected. sr[6] framing error (fe) this bit indicates that a stop bit was not detected when an otherwise nonzeros data character (including parity, if enabled) was received. the stop bit check is made in the middle of the first stop bit position. sr[5] parity error (pe) this bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the fifo was received with incorrect parity. in the special 'wake up mode', the parity error bit stores the received a/d bit. sr[4] overrun error (oe) this bit, when set, indicates that one or more characters in the received data stream have been lost. it is set upon receipt of the start bit of a new character when the rxfifo is full and a character is already in the receive shift register (257 valid characters in the receiver) waiting for an empty fifo position. when this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. this bit is cleared by a reset error status command. sr [3] transmitter idle (tx idle) this bit is set when the transmitter underruns, i.e., both the txfifo and the transmit shift register are empty. it is set after transmission of the last stop bit of a character, if no character is in the txfifo awaiting transmission. it is negated when the txfifo is loaded by the cpu, or when the transmitter is disabled or reset. this bit is concerned with the transmitter transmitting data and it essentially shows a transmitter underruno. if, while it is underrun it is commanded to send an x on/xoff character it will remain at the zero state. if it is underrun and while sending an xon/xoff character the txfifo is loaded then the bit will go low. sr[2] transmitter ready (txrdy) this bit, when set, indicates that the txfifo is ready to be loaded with at least one more character. this bit is cleared when the txfifo is full or is above its interrupt threshold level set in the mr registers or txfifo interrupt fill level register (txfil). characters loaded in the txfifo while the transmitter is disabled will not be transmitted. sr[1] rxfifo full (rxfull) this bit is set when a character is transferred from the receive shift register to the receive fifo and the transfer causes the fifo to become full, i.e., all 256 rxfifo positions are occupied. it is reset when the cpu reads the rxfifo and that read leaves one or more empty byte position(s). if a character is waiting in the receive shift register because the rxfifo is full, rxfull is not reset until the second read of the rxfifo since the waiting character is immediately loaded to the rxfifo. sr[0] receiver ready (rxrdy) this bit indicates that a character has been received and is waiting in the rxfifo to be read by the cpu. it is set when the character is transferred from the receive shift register to the rxfifo and reset when the cpu reads the rxfifo, and no more characters are in the rxfifo.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 30 isr interrupt status register a and b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o port change of state receiver watchdog timeout address recognition event xon/off event c/t ready break change of state rxint receiver entered the arbitration process. txint transmitter entered the arbitration process. this register provides the status of all potential interrupt sources for a uart channel. when generating an interrupt arbitration value, the contents of this register are masked by the interrupt mask register (imr). if a bit in the isr is a '1' and the corresponding bit in the imr is also a `1'; interrupt arbitration for this source will begin. if the corresponding bit in the imr is a zero, the state of the bit in the isr can have no affect on the irqn output. note that the imr may or may not mask the reading of the isr as determined by gccr[06]. if gccr[0] is cleared, the reset and power on default, the isr is read without modification. if gccr[0] is set, the read of the isr gives a value of the isr anded with the imr. isr[7] input change of state. this bit is set when a change of state occurs at the i/o1 or i/o0 input pins. it is reset when the cpu reads the input port register, ipr. isr[6] fixed watchdog timeout. this bit is set when the receiver's watchdog timer has counted more than 64 bit times since the last rxfifo event. rxfifo events are a read of the rxfifo or grxfifo, or the load of a received character into the fifo. the interrupt will be cleared automatically when the rxfifo or grxfifo is read. the receiver watchdog timer is included to allow detection of the very last characters of a received message that may be waiting in the rxfifo, but are too few in number to successfully initiate an interrupt. refer to the watchdog timer description for details of how the interrupt system works after a watchdog timeout. isr[5] address recognition status change. this bit is set when a change in receiver state has occurred due to an address character being received from an external source and matches the reference address in arcr. the bit and interrupt is negated by a write to the cr with command x11011, reset address recognition status. isr[4] xon/xoff status change. this bit is set when a xon/xoff character being received from an external source. the bit is negated by a read of the channel xon/xoff interrupt status register, xisr. isr[3] counter timer status the c/t has timed out or the count passed through 0. this bit is cleared by issuing the astop c/t o command. isr[2] change in channel break status. this bit, when set, indicates that the receiver has detected the beginning or the end of a received break. it is reset when the cpu issues a reset break change interrupt command via the cr. isr[1] rxint. (also rx dma hand shake at i/o pins) the general function of this bit is to indicate that the rxfifo has data available and that it has entered the arbitration process. the particular meaning of this bit is programmed by rxfil register. if programmed as receiver ready (mr2[3:2] = 00), it indicates that at least one character has been received and is waiting in the rxfifo to be read by the host cpu. it is set when the character is transferred from the receive shift register to the rxfifo and reset when the cpu reads the last character from the rxfifo. if rxfil is programmed as fifo full, isr[1] is set when a character is transferred from the receive holding register to the rxfifo and the transfer causes the rxfifo to become full, i.e. all 256 fifo positions are occupied. it is reset whenever rxfifo is not full. if there is a character waiting in the receive shift register because the fifo is full, the bit is set again when the waiting character is transferred into the fifo. the other two conditions of these bits, 3/4 and half full operate in a similar manner. the isr[1] bit is set when the rxfifo fill level meets or exceeds the value; it is reset when the fill level is less. see the description of the mr2 register. note : this bit must be at a one (1) for the receiver to enter the arbitration process. it is the fact that this bit is zero (0) when the rxfifo is empty that stops an empty fifo from entering the interrupt arbitration. also note that the meaning if this bit is not quite the same as the similar bit in the status register (sr). isr[0] txint. (also tx dma hand shake at i/o pins) the general function of this bit is to indicate that the txfifo has an at least one empty space for data. the particular meaning of the bit is controlled by mr0 [5:4] indicates the txfifo may be loaded with one or more characters. if mr0[5:4] = 00 (the default condition) this bit will not set until the txfifo is empty 256 bytes available. if the fill level of the txfifo is below the trigger level programmed by the txint field of the mode register 0, this bit will be set. a one in this position indicates that at least one character can be sent to the txfifo. it is turned off as the txfifo is filled above the level programmed by mr0[5:4. this bit turns on as the fifo empties. (note that the rxfifo bit turns on as the fifo fills.) this often a point of confusion in programming interrupt functions for the receiver and transmitter fifos. note : this bit must be at a one (1) for the transmitter to enter the arbitration process. it is the fact that this bit is zero (0) when the txfifo is full that stops a full txfifo from entering the interrupt arbitration. also note that the meaning if this bit is not quite the same as the similar bit in the status register (sr).
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 31 imr interrupt mask register a and b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o port change of state rx watchdog timeout address recognition event xon/off event c/t ready break change of state rxrdy interrupt txrdy interrupt the programming of this register selects which bits in the isr cause an interrupt output. if a bit in the isr is a '1' and the corresponding bit in the imr is a '1', the interrupt source is presented to the internal interrupt arbitration circuits, eventually resulting in the irqn output being asserted (low). if the corresponding bit in the imr is a zero, the state of the bit in the isr has no affect on the irqn output. imr[7] cos enable allows a change of state in the inputs equipped with input change detectors to cause an interrupt. imr[6] fixed watchdog enable controls the generation of an interrupt watchdog timer event. if set, a count of 64 idle bit times in the receiver will begin interrupt arbitration. imr[5] address recognition enable enables the generation of an interrupt in response to changes in the address recognition circuitry of the special mode (multidrop or wakeup mode). imr[4] xon/xoff enable enables the generation of an interrupt in response to recognition of an inband flow control character. imr[3] counter/timer enable enable the c/t interrupt when the c/t reaches 0 count. [2] enables the generation of an interrupt when a break condition has been detected by the channel receiver. imr[1] receiver (rx) enable enables the generation of an interrupt when servicing for the rxfifo is desired. imr[0] transmitter (tx) enable enables the generation of an interrupt when servicing for the txfifo is desired. rxfifo receiver fifo, a and b bit[10] bit[9] bit[8] bits [7:0] these bits are sent to the status register this the data byte sent to the data bus or rxfifo read break received status framing error status parity error status 8 data bits msbs =0 for 7,6,5 bit data the fifo for the receiver is 11 bits wide and 256 owordso deep. the status of each byte received is stored with that byte and is moved along with the byte as the characters are read from the fifo. the upper three bits are presented in the status register and they change in the status register each time a data byte is read from the fifo. therefor the status register should be read before the byte is read from the rxfifo if one wishes to ascertain the quality of the byte the foregoing applies to the ocharacter erroro mode of status reporting. see mr1[5] and orxfifo statuso descriptions for oblock erroro status reporting. briefly, oblock erroro gives the accumulated error of all bytes received by the rxfifo since the last areset erroro command was issued. (cr = 0x04) txfifo transmitter fifo, a and b bits 7:0 8 data bits. msbs set to 0 for 7, 6, 5 bit data the fifo for the transmitter is 8 bits wide by 256 bytes deep. for character lengths less than 8 bits the upper bits will be ig nored by the transmitter state machine and thus are effectively discarded. rxfil receiver fifo interrupt level, a and b bits 7:0 any one of 256 fifo fill positions the position in the rx fifo that causes the receiver will enter the interrupt arbitration process. this register is used to off set the effect of the arbitration threshold. it use may yield moderate improvements in the interrupt service. it will also aequalizeo interrupt laten cy and allow for larger aggregate block transfers between fast and slow channels. writing to this register removes the interrupt control established in mr0 and mr1. rxfl receiver fifo fill level register bits 7:0 channel byte count code ** (1) = implied `1' 00000001 = 1 00000010 = 2 to 11111111 = 255 **(1)00000000 = 256 if rxrdy status bit is set. the number of bytes filled in the receiver fifo
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 32 txfil transmitter fifo interrupt level a and b bits 7:0 any one of 256 fifo empty positions the position in the tx fifo that caused the transmitter will enter the interrupt arbitration process. this register is used to offset the effect of the arbitration threshold. it use may yield moderate improvements in the interrupt service. it will also aequalizeo interrupt laten cy and allow for larger aggregate block transfers between fast and slow channels. writing to this register removes the interrupt control established in mr0 and mr1. txel transmitter fifo empty level register bits 7:0 channel byte count code ** (1) = implied `1' 00000001 = 1 00000010 = 2 to 11111111 = 255 **(1)00000000 = 256 if txrdy status bit is set. the number of empty bytes in the transmitter fifo registers for character recognition xoncr xon/xoff character register a and b bits 7:0 8 bits of the xon character recognition (resets to 0x11) an 8bit character register that contains the compare value for a xon character. xoffcr xoff character register a and b bits 7:0 8 bits of the xoff character recognition (resets to 0x13) an 8bit character register that contains the compare value for a xoff character. arcr address recognition character register a and b bits 7:0 8 bits of the multidrop address character recognition (resets to 0x00) an 8 bit character register that contains the compare value for the wakeup address character
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 33 xisr xonxoff interrupt status register a and b (reading this register clears xisr(7:4)) bits 7:6 bits 5:4 bits 3:2 bits 1:0 received x character status automatic x character transmission status txd flow status txd character status 00 = none 01 = xoff received 10 = xon received 11 = both received 00 = none 01 = xon transmitted 10 = xoff transmitted 11 = both transmitted 00 = normal transmission 01 = txd halt pending 10 = re enabled 11 = flow halted 00 = normal txd data 01 = idle wait for fifo data 10 = xoff in pending 11 = xon in pending xisr[7:6] received x character status. this field can be read to determine if the receiver has encountered a xon or xoff character in the incoming data stream. these bits are maintained until a read of the xisr. the field is updated by x character reception regardless of the state of mr3(7) and mr3(3:2) or imr(4). the field can therefore be used as a character detector for the bit patterns stored in the xon and xoff character registers. xisr[5:4] automatic transmission status. this field indicates the last flow control character sent in the auto receiver flow control mode. if auto receiver mode has not been enabled, this field will always read b'00. it will likewise reset to b'00 if mr0(3) is reset. if the auto receiver mode is exited while this field reads b'10, it is the user's responsibility to transmit a xon, when appropriate. xisr[3:2] txd condition of the automatic flow control status. this field tracks the transmitter's flow status as follows: ? 00 n ormal transmission. transmitter is not affected by xon or xoff. ? 01 txd halt pending. after the current character finishes the transmitter will stop. the status will then change to b'11. ? 10 r eenabled. the transmitter had been halted and has been restarted. it is sending (or is prepared to send) data characters. after a read of the xisr, it will return to onormalo status. ? 11 the transmitter is stopped due to an xoff character being received from its associated receiver. the transmitter is aflow controlledo. xisr[1:0] txd x character status. this field allows determination of the type of character being transmitted. it will always be b'00 if none of the automatic x character controls of mr3[3:2] is enabled. ? 01 the channel is waiting for a data character to transfer from the txfifo. this condition will only occur for a bit time after a xon or xoff character transmission unless the txfifo is empty. ? 10 a command to send an xoff character is pending. ? 11 a command to send an xon character is pending. conditions b'10 and b'11 will not exist for more than a character time. wcxer watch dog, character, address and x enable register a and b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 watch dog * address recognition xon recognition xoff recognition 1 = disable wd 0 = no action 1 = enable wd 0 = no action 1 = disable ar 0 = no action 1 = enable ar 0 = no action 1 = disable xon 0 = no action 1 = enable xon 0 = no action 1 = disable xoff 0 = no action 1 = enable xoff 0 = no action this register enables the uart's character recognition, address recognition and receiver watchdog timer. if both enable and disable are active a disable results. this register is used to enable the generalpurpose character recognition feature without causing any xon/xoff or wakeup mode activities to occur. the recognition event is reported in the isr register. * this bit control is duplicated at mr0[7].
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 34 programmable counters, timers and baud rate generators pbrgpu programmable brg timer reload registers, upper 0 and 1 bits 7:0 8 msbs of the brg timer divisor. this is the upper byte of the 16bit value used by the brg timer in generating a baud rate clock pbrgpl programmable brg timer reload registers, lower 0 and 1 bits 7:0 8 lsb of the brg timer divisor. this is the lower byte of the 16bit value used by the brg timer in generating a baud rate clock. ctcs 0 and 1 counter timer clock source note : writing to this register removes the control established in the counter/timer portion of the acr in the default register map bit 7:6 bit 5:4 bit 3:0 reserved mode control clock selection 00 selects counter mode. generates a timing edge 01 selects timer mode. generates a square wave 10 reserved 11 selects timer pulse mode. generates periodic pulses twice the frequency as in timer mode. pulse width is one cycle of the clock as it is delivered to the c/t. (i.e. after any prescale) 0000 external i/o2 a (for ct 0), i/o7 a (for ct 1) 0001 external i/o2 a/16 (for ct 0), i/o7 a/16 (for ct 1) 0010 sclk 0011 sclk / 2 0100 sclk / 16 0101 sclk / 32 0110 sclk / 64 0111 sclk / 128 txc1x a txc1x b 1010, 1011 reserved 1100 rx character count (ch a) clock is rxfifo a load pulse 1101 rx character count (ch b) clock is rxfifo b load pulse 1110, 1111 reserved ctvu counter timer value registers, upper 0 and 1 bits 7:0 8 msbs of the counter timer preset value reading this register gives the value of the upper 8 bits of the counter timer ctvl counter timer value registers, lower 0 and 1 bits 7:0 8 lsb of the counter timer preset value reading this register gives the value of the upper 8 bits of the counter timer note : the counter timer should be stopped before reading. usually the clock of the counter timer is not synchronized with the read of the c/t. it is therefore possible to capture changing data during the read. depending on the clock speed with respect to the read cycle this could be made worse or completely eliminated. if the stop counter command is issued and following that the c/t is read there will be no uncertainty go its value. if it is necessary to read the c/t aon the flyo then reading it twice and comparing the values will correct the problem. the double read will not be effective if the counter timer clock is faster than a read cycle. pbrgcs programmable brg clock source bit 7 bit 6:4 bit 3 bit 2:0 pbrg 1, register control pbrg 1, clock selection pbrg 0, register control pbrg 0, clock selection 0 = resets pbrg 1 and holds it stopped 1 = allows pbrg 1 to run. 000 = sclk 001 = sclk / 2 010 = sclk/ 16 011 = sclk / 32 100 = sclk / 64 101 = sclk / 128 110 = i/o4 a 111 = reserved 0 = resets pbrg 0 and holds it stopped. 1 = allows pbrg 0 to run. 000 = sclk 001 = sclk / 2 010 = sclk / 16 011 = sclk / 32 100 = sclk / 64 101 = sclk / 128 110 = i/o3 a 111 = reserved start/stop control and clock select register for the two brg counters. the clock selection is for the input to the counters. it is that clock divided by the number represented by the pbrgpu and pbrgpl the will be used as the 16x clock for the receivers and transmitters. when the brg timer clock is selected for the receiver(s) or transmitter(s) the receivers and transmitters will consider it as a 16x clock and further device it by 16. in other words the receivers and transmitters will always be in the 16x ode of operation when the internal brg timer is selected for their clock.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 35 ctpu counter timer preset upper 0 and 1 ctpu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the lower eight (8) bits for the 16 bit counter timer preset register ctpl counter timer preset low 0 and 1 ctpl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the upper eight (8) bits for the 16 bit counter timer preset register the ctpu and ctpl hold the eight msbs and eight lsbs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. the minimum value that may be loaded into the ctpu/ctpl registers is h`0000'. note that these registers are writeonly and cannot be read by the cpu. in the timer mode, the c/t generates a square wave whose period is twice the value (in c/t clock periods) of the ctpu and ctpl. the waveform so generated is often used for a data clock. the formula for calculating the divisor n to load to the ctpu and ctpl for a particular 1x data clock is shown below. note : the 2 in the denominator is for the square wave generation. for the pulse mode change the 2 to a 1. n clockinputfrequency (2 16 (baud rate desired)) often this division will result in a noninteger number, 26.3 for example. one can only program integer numbers in a digital divider. therefore, 26 would be chosen. this gives a baud rate error of 0.3/26.3, which is 1.14% and well within the ability asynchronous mode of operation. if the value in ctpu and ctpl is changed, the current halfperiod will not be affected, but subsequent half periods will be. the c/t will not be running until it receives an initial `start counter' command from the command register (or a read at address a6a0 = 0001110 in the lower 16 position address space) . after this, while in timer mode, the c/t will run continuously. receipt of a start counter command causes the counter to terminate the current timing cycle and to begin a new cycle using the values in ctpu and ctpl. the counter ready status bit (isr [3]) is set once each cycle of the square wave. the bit is reset by a stop counter command from the command register (or a read with a6a0 = 0x0f in the lower 16 position address space). the command however, does not stop the c/t. the generated square wave is output on i/o3 if it is programmed to be the c/t output. in the counter mode, the value c/t loaded into ctpu and ctpl by the cpu is counted down to 0. counting begins upon receipt of a start counter command. upon reaching terminal count h`0000', the counter ready interrupt bit (isr [3]) is set. the counter continues counting past the terminal count until stopped by the cpu. if i/o3 is programmed to be the output of the c/t, the output remains high until terminal count is reached; at which time it goes low. the output returns to the high state and isr [3] is cleared when the counter is stopped by a stop counter command. the cpu may change the values of ctpu and ctpl at any time, but the new count becomes effective only on the next start counter commands. if new values have not been loaded, the previous count values are preserved and used for the next count cycle in the counter mode, the current value of the upper and lower 8 bits of the counter (ctpu, ctpl) may be read by the cpu. it is recommended that the counter be stopped when reading to prevent potential problems that may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. however, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in ctpu and ctpl. when the c/t clock divided by 16 is selected, the maximum divisor becomes 1,048,575. the cts, rts, cts enable tx signals cts (clear to send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. the cts input is on pin i/o0 a for tx a and on i/o1 a for tx b. the cts signal is active low; thus; it is called ctsn a for tx a and ctsn b for tx b. rts is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. it is also active low and is, thus, called rtsn a for rx a and rtsn b for rx b. rtsn a is on pin i/o0 b and rtsn b is on i/o1 b. a receiver's rtsn output will usually be connected to the cts input of the associated transmitter. therefore, one could say that rts and cts are different ends of the same wire! mr2 (4) is the bit that allows the transmitter to be controlled by the cts pin (i/o0 a or i/o1 a). when this bit is set to one and the cts input is driven high, the transmitter will stop sending data at the end of the present character being serialized. it is usually the rts output of the receiver that will be connected to the transmitter's cts input. the receiver will set rts high when the receiver fifo is full and the start bit of the ninth character is sensed. transmission then stops with nine valid characters in the receiver. when mr2 (4) is set to one, ctsn must be at zero for the transmitter to operate. if mr2 (4) is set to zero, the i/o pin will have no effect on the operation of the transmitter. mr1 (7) is the bit that allows the receiver to control i/o0 b. when the receiver controls i/o0 b (or i/o1 b), the meaning of that pin will be the rtsn function.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 36 registers of the arbitrating interrupt system and bidding control icr interrupt control register bits 7:0 upper eight bits of the arbitration threshold this register provides a single 8bit field called the interrupt threshold for use by the interrupt arbiter. the field is interpreted as a single unsigned integer. the interrupt arbiter will not generate an external interrupt request, by asserting irqn, unless the value of the highest priority interrupt exceeds the value of the interrupt threshold. if the highest bidder in the interrupt arbitration is lower than the threshold level set by the icr, the current interrupt register, cir, will contain 0x'00. refer to the functional description of interrupt generation for details on how the various interrupt source bid values are calculated. note : while a watchdog timer interrupt is pending, the icr is not used and only receiver codes are presented for interrupt arbitration. this allows receivers with very low count values (perhaps below the threshold value) to win interrupt arbitration without requiring the user to explicitly lower the threshold level in the icr. these bits are the upper seven (8) bits of the interrupt arbitration system. the lower three (3) bits represent the channel number. ucir update cir a command based upon a decode of address 0x8c. (ucir is not a register!) a write (the write data is not important; a adon't careo) to this 'register' causes the current interrupt register to be updated with the value that is winning interrupt arbitration. the register would be used in systems that polls the interrupt status registers rather than wait for interrupts. alternatively, the cir is normally updated during an interrupt acknowledge bus cycle in interrupt driven systems. cir current interrupt register bits 7:6 bits 5:1 bits 0 type current byte count/type channel number or c/t number 00 = type other than transmit or receiver 00000 = no interrupt 00001 = change of state 00010 = address recognition 00011 = xon/xoff status 00100 = receiver watch dog 00101 = break change 00110 = counter timer 00111 = rx loop back error 0 = channel a or c/t 0 1 = channel b or c/t 1 01 = transmit 11 = receive w errors 10 = receive w/o errors current count code 00000 => at least 1 character 00001 => at least 16 characters 00001 => at least 24 characters . . 11101 => at least 240 characters 11110 => at least 248 characters 11111 => 256 (see also gibcr) 0 = a 1 = b the current interrupt register is provided to speed up the specification of the interrupting condition in the duart. the cir is updated at the beginning of an interrupt acknowledge bus cycle or in response to an update cir command. (see immediately above) although interrupt arbitration continues in the background, the current interrupt information remains frozen in the cir until another iackn cycle or update cir command occurs. the lsbs of the cir provide part of the addressing for various global interrupt registers including the gibcr, gicr, gitr and the global rxfifo and txfifo fifo. the host cpu need not generate individual addresses for this information since the interrupt context will remain stable at the fixed addresses of the global interrupt registers until the cir is updated. for most interrupting sources, the data available in the cir alone will be sufficient to set up a service routine. the cir may be processed as follows: if cir[7] = 1, then a receiver interrupt is pending and the count is cir[5:1], channel is cir[0] else if cir[6] = 1 then a transmitter interrupt is pending and the count is cir[5:1], channel is cir[0] else the interrupt is another type, specified in cir[5:1] note : the gibcr, global interrupting byte count register, may be read to determine an exact character count. ivr interrupt vector register bits 7:0 8 data bits of the interrupt vector (ivr) the ivr contains the byte that will be placed on the data bus during an iackn cycle when the gccr bits (2:1) are set to binary `01'. this is the unmodified form of the interrupt vector.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 37 modification of the ivr bits 7:3 bits 2:1 bit 0 always contains bits (7:3) of the ivr will be replaced with current interrupt type if ivc field of gccr = 3 replaced with interrupting channel number if ivc field of gccr > 1 the table above indicates how the ivr may be modified by the interrupting source. the modification of the ivr as it is presente d to the data bus during an iack cycle is controlled by the setting of the bits (2:1) in the gccr (global chip configuration register). gicr global interrupting channel register bits 7:1 bit 0 reserved channel code 0 = a 1 = b a register associated with the interrupting channel as defined in the cir. it contains the channel number for the interrupting channel. gibcr global interrupting byte count register bits 7:0 channel byte count code 00000001 = 1 00000010 = 2 . 11111111 = 255 00000000 = 256 a register associated with the interrupting channel as defined in the cir. its numerical value equals txel or rxfl at the time iackn or aupdate ciro command was issued . the true number of bytes ready for transfer to the transmitter or transfer from the receiver. it is undefined for other types of interrupts gitr global interrupting type register bit 7:6 bit 5 bit 4:3 bit 2:0 receiver interrupt transmitter interrupt reserved other types 0x = not receiver 10 = with receive errors 11 = w/o receive errors 0 = not transmitter 1 = transmitter interrupt read 0x00 000 = not oothero type 001 = change of state 010 = address recognition event 011 = xon/xoff status 100 = rx watchdog 101 = break change 110 = counter timer 111 = rx loop back error a register associated with the interrupting channel as defined in the cir. it contains the type of interrupt code for all inter rupts. grxfifo global rxfifo register bits 7:0 8 data bits of rxfifo. msbs set to 0 for 7, 6, 5 bit data the rxfifo of the channel indicated in the cir channel field. undefined when the cir interrupt context is not a receiver interr upt. global txfifo register gtxfifo global txfifo register bits 7:0 8 data bits of txfifo. msbs not used for 7, 6, 5 bit data the txfifo of the channel indicated in the cir channel field. undefined when the cir interrupt context is not a transmitter int errupt. writing to the gtxfifo when the current interrupt is not a transmitter event may result in the characters being transmitted on a different channel than intended. bcrbrk bidding control register break change, a and b bits 7:0 msbs of break change interrupt bid this register provides the 8 msbs of the interrupt arbitration number for a break change interrupt. bcrcos bidding control register change of state, a and b bits 7:0 msbs of change of state detectors (cos) interrupt bid this register provides the 8 msbs of the interrupt arbitration number for a change of state, cos, interrupt.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 38 bcrx bidding control register xon/xoff, a and b bits 7:0 msbs of an xon/xoff interrupt bid this register provides the 8 msbs of the interrupt arbitration number for a xon/xoff interrupt. bcra bidding control register address, a and b bits 7:0 msbs of an address recognition event interrupt bid this register provides the 8 msbs of the interrupt arbitration number for an address recognition event interrupt. bcr c/t bidding control register c/t, 0 and 1 bits 7:0 msbs of a counter/timer event interrupt bid this register provides the 8 msbs of the interrupt arbitration number for a counter/timer event interrupt. bcrlbe bidding control register received loop back error bits 7:0 msbs of a received loop back error event interrupt bid this register provides the 8 msbs of the interrupt arbitration number for the received loop back error interrupt. registers of the i/o ports ipcrl input port change register lower nibble, a and b (n = a for a, n = b for b) bit 7 bit 6 bit 7 bit 6 bit 3 bit 2 bit 1 bit 0 d i/o3 n change d i/o2 n change d i/o1 n change d i/o0 n change i/o3 n state i/o2 n state i/o1 n state i/o0 n state 0 = no change 1 = change 0 = no change 1 = change 0 = no change 1 = change 0 = no change 1 = change reads the actual logic level at the pin. 1 = high level; 0 = low level this register may be read to determine the current logical level of the i/o pins and examine the output of the change detectors assigned to each pin. if the change detection is not enabled or if the pin is configured as an output, the associated change field will read b'0 . ipcru input port change register upper nibble, a and b (n = a for a, n = b for b) bit 7 bit 6 bit 7 bit 6 bit 3 bit 2 bit 1 bit 0 d i/o7 n change d i/o6 n change d i/o5 n change d i/o4 n change i/o7 n state i/0n6 state i/o5 n state i/o4 n state 0 = no change 1 = change 0 = no change 1 = change 0 = no change 1 = change 0 = no change 1 = change reads the actual logic level at the pin. 1 = high level; 0 = low level this register may be read to determine the current logical level of the i/o pins and examine the output of the change detectors assigned to each pin. if the change detection is not enabled or if the pin is configured as an output, the associated change field will read b'0 . ipr input port register, a and b (n = a for a, n = b for b) bits 7:0 logical levels of i/o(7:0)n ipce input change detect enable, a and b (n = a for a, n = b for b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d i/o7 n enable d i/o6 n enable d i/o5 n enable d i/o4 n enable d i/o3 n enable d i/o2 n enable d i/o1 n enable d i/o0 n enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable ipce[7:0] bits activate the input change of state detectors. if a pin is configured as an output, the change of state detectors , if enabled, continue to be active and will show a change of state as the i/p port changes.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 39 i/opcr 0 i/o port configuration register bits 7:6 bits 5:4 bits 3:2 bits 1:0 i/o3 a control i/o2 a control i/o1 a control i/o0 a control 00 = gpi / txc a 01 = opr[3] a 10 = txc a (16x) output 11 = reserved 00 = gpi / ct 0 clock input 01 = opr[2] a / dtrn a 10 = txc a (1x) output 11 = reserved 00 = gpi / ctsn b 01 = opr[1] a 10 11 = reserved 00 = gpi / ctsn a 01 = opr[0] a 10 11 = reserved i/opcr 1 i/o port configuration register bits 7:6 bits 5:4 bits 3:2 bits 1:0 i/o7 a control i/o6 a control i/o5 a control i/o4 a control 00 = gpi / ct 1 clock input 01 = opr[7] a / dtrn b 10 = txc b (1x) output 11 = reserved 00 = gpi / rxc b / pbrg 1 clk input 01 = opr[6] a 10 = rxc b (16x) output 11 = reserved 00 = gpi / txc b 01 = opr[5] a 10 = txc b (16x) output 11 = reserved 00 = gpi / rxc a / pbrg 0 clk input 01 = opr[4] a 10 = rxc a (16x) output 11 = reserved i/opcr 2 i/o port configuration register bits 7:6 bits 5:4 bits 3:2 bits 1:0 i/o3 b control i/o2 b control i/o1 b control i/o0 b control 00 = gpi /dsrn b 01 = opr[3] b 10 = rxc b (1x) output 11 = c/t 0 output (open drain) 00 = gpi /dsrn a 01 = opr[2] b 10 = rxc a (1x) output 11 = c/t 1 output (open drain) 00 = gpi 01 = opr[1] b / rtsn b 10 = reserved 11 = reserved 00 = gpi 01 = opr[0] b / rtsn b 10 = reserved 11 = reserved i/opcr 3 i/o port configuration register bits 7:6 bits 5:4 bits 3:2 bits 1:0 i/o7 b control i/o6 b control i/o5 b control i/o4 b control 00 = gpi /rin b 01 = opr[7] b 10 =txintn b (open drain) 11 =reserved 00 = gpi /rin a 01 = opr[6] b 10 =txintn a (open drain) 11 = reserved 00 = gpi /dcdn b 01 = opr[5] b 10 = rxintn b (open drain) 11 = reserved 00 = gpi /dcdn a 01 = opr[4] b 10 = rxintn a (open drain) 11 = reversed note : both i/o port a and b default to input upon a hardware reset to avoid hardware conflicts with i/o direction the four registers above contain 4, 2 bit fields that set the direction and source for each of the i/o pins associated with the channel. the i/o0 b or i/o1 b output may be rtsn if mr1[7] is set. it may also signal oend of transmissiono if mr2[5] is set. (please see the descr iptions of these functions under the mr1 and mr2 register descriptions). the binary settings of the binary 00 combination always configures the i/o pins as ainputso. however the input circuit of the i /o pins are always active. in actuality the binary 00 condition only disable the output driver of the pin. since the input circuit and the associated change of state detector is always active the output signal may generate interrupts or drive counters. this register resets to 0x00 on reset, effectively configuring all i/o pins as inputs. inputs may be used as rxc, txc inputs or ctsn and general purpose inputs simultaneously. all inputs are equipped with change detectors that may be used to generate interrupts or can be polled, as required. sopr a and sopr b set the output port bits (opr a and opr b) sopr [7:0] ones in the byte written to this register will cause the corresponding bit positions in the opr to set to 1. zeros have no effect. this allows software to set individual bits with our keeping a copy of the opr bit configuration. one register for each channel. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set opr bits opr 7 opr 6 opr 5 opr 4 opr 3 opr 2 opr 1 opr 0 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 40 ropr a and ropr b reset ropr output port bits (opr a and opr b) ropr [7:0] ones in the byte written to the ropr will cause the corresponding bit positions in the opr to set to 0. zeros have no effect. this allows software to reset individual bits with our keeping a copy of the opr bit configuration. one register for each channel bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset opr bits opr 7 opr 6 opr 5 opr 4 opr 3 opr 2 opr 1 opr 0 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change opr output port register, a and b (n = a for a, n = b for b) the output pins (i/o pins) drive the data written to this register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 opr i/o7 n i/o6 n i/o5 n i/o4 n i/o3 n i/o2 n i/o1 n i/o0 n 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low this register is set by the sopr and ropr above. the registers for compatibility with previous duarts the purpose of including previous functionality is to allow users to call communications code that may be used in former systems. when the registers in this lower 16position address space is used it will revoke programming done in the upper address space where the addresses are duplicated. if functions have been called from upper address space that do not exist in the lower address space they will remain active. it is therefore recommended that the areset to c92 a command be issued before calling code written for older devices. this is just recommended. if one wishes to enhance previous code by using xon/xoff, for example, there is no restriction against it. these registers provide the original functionality of previous philips duarts: scn2681, scn68681, scc2691, scc68692, sc26c92 and sc28l92. table 7. sc28l92 register addressing read (rdn = 0) write (wrn = 0) address read (rdn = 0) write (wrn = 0) 0 0 0 0 mode register a (mr0 a, mr1 a, mr2 a) mode register a (mr0 a, mr1 a, mr2 a) 0 0 0 1 status register a (sr a) clock select register a (csr a ) 0 0 1 0 reserved command register a (cr a) 0 0 1 1 rx holding register a (rxfifo a) tx holding register a (txfifo a) 0 1 0 0 input port change register (ipcr) aux. control register (acr) 0 1 0 1 interrupt status register (isr) interrupt mask register (imr) 0 1 1 0 counter/timer upper (ctpu) c/t upper preset register (ctpu) 0 1 1 1 counter/timer lower (ctpl) c/t lower preset register (ctpl) 1 0 0 0 mode register b (mr0 b, mr1 b, mr2 b) mode register b (mr0 b, mr1 b, mr2 b) 1 0 0 1 status register b (sr b) clock select register b (csr b ) 1 0 1 0 reserved command register b (cr b) 1 0 1 1 rx holding register b (rxfifo b) tx holding register b (txfifo b) 1 1 0 0 ivr or general purpose register ivr or general purpose register 1 1 0 1 input port (ipr) i/o(6:0) a output port confide. register (opcr) i/o(7:2) b 1 1 1 0 start counter command (c/t 0) set output port bits command (sopr) i /o(7:0) b 1 1 1 1 stop counter command (c/t 0) reset output port bits command (ropr) i/o(7:0) b note: the three mr registers are accessed via the mr pointer and commands 0x1n and 0xbn (where n = represents receiver and transmitter enable bits)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 41 the following registers are unique for each channel mode register mrn a mrn b r/w status register sr a sr b r only clock select csr a csr b w only command register cr a cr b w only receiver fifo rxfifo a rxfifo b r only transmitter fifo txfifo a txfifo b w only these registers support functions for both channels input port change register ipcr r auxiliary control register acr w interrupt status register isr r interrupt mask register imr w counter timer upper value ctpu r counter timer lower value ctpl r counter timer preset upper ctpu w counter timer preset lower ctpl w input port register ipr r output configuration register opcr w set output port bits w reset output port bits w table 8. baud rate generator characteristics crystal or clock = 14.7456 mhz normal rate (baud) actual 16x clock (khz) error (%) normal rate (baud) actual 16x clock (khz) error (%) 50 0.8 0 2400 38.4 0 75 1.2 0 4800 76.8 0 110 1.759 0.069 7200 115.2 0 134.5 2.153 0.059 9600 153.6 0 150 2.4 0 19.2k 307.2 0 200 3.2 0 38.4k 614.4 0 300 4.8 0 14.4k 230.4 0 600 9.6 0 28.8k 460.8 0 1050 16.756 0.260 31.25 500.0 1.6 1200 19.2 0 57.6k 921.6 0 1800 28.8 0 115.2k 1843.2 0 2000 32.056 0.175 230.4k 3686.4 0 note: duty cycle of 16x clock is 50% 1%
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 42 register descriptions mode registers mr0 mode register 0 mr0 is accessed by setting the mr pointer to 0 via the command register command b. bit 7 bit 6 bit (5:4) bit 3 bit 2 bit 1 bit 0 mr0 a mr0 b mr0 b[3:0] are reserved rx watch dog 0 = disable 1 = enable rxint bit 2 see tables in mr0 description txint (1:0) see table #4 fifo size 0 = 8 1 = 256 baud rate extended ii 0 = norma 1 = extend ii test 2 set to 0 baud rate extended 1 0 = normal 1 = extend mr0[7] this bit controls the receiver watchdog timer. 0 = disable, 1 = enable. when enabled, the watch dog timer will generate a receiver interrupt if the receiver fifo has not been accessed within 64 bit times of the receiver 1x clock. this is used to alert the control processor that data is in the rxfifo that has not been read. this situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. this control bit is duplicated wcxer(7:6) mr0[6] bit 2 of receiver fifo interrupt level. this bit along with bit 6 of mr1 sets the fill level of the 8 byte fifo that generates the receiver interrupt. mr0[6] mr1[6] note that this control is split between mr0 and mr1. this is for backward compatibility to the sc2692 and scn2681. table 9. receiver fifo interrupt fill level mr0(3)=0 mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rx rdy) 01 3 or more bytes in fifo 10 6 or more bytes in fifo 11 8 bytes in fifo (rx full) table 10. receiver fifo interrupt fill level mr0(3)=1 mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rx rdy) 01 128 or more bytes in fifo 10 192 or more bytes in fifo 11 256 bytes in fifo (rx full) for the receiver these bits control the number of fifo positions empty when the receiver will attempt to interrupt. after the reset the receiver fifo is empty. the default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it. mr0[5:4] tx interrupt fill level. table 11. transmitter fifo interrupt fill level mr0(3)=0 mr0[5:4] interrupt condition 00 8 bytes empty (tx empty) 01 4 or more bytes empty 10 6 or more bytes empty 11 1 or more bytes empty (tx rdy) table 12. transmitter fifo interrupt fill level mr0(3)=1 mr0[5:4] interrupt condition 00 256 bytes empty (tx empty) 01 128 or more bytes empty 10 192 or more bytes empty 11 1 or more bytes empty (tx rdy) for the transmitter these bits control the number of fifo positions empty when the receiver will attempt to interrupt. after the reset the transmit fifo has 8 bytes empty. it will then attempt to interrupt as soon as the transmitter is enabled. the default setting of the mr0 bits (00) condition the transmitter to attempt to interrupt only when it is completely empty. as soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request. mr0[3] fifo size mr0[2:0] these bits are used to select one of the sixbaud rate groups. see table 13 for the group organization. ? 000 normal mode ? 001 extended mode i ? 100 extended mode ii other combinations of mr2[2:0] should not be used note : mr0[3:0] are not used in channel b and should be set to 0.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 43 mr1 mode register 1 bit 7 bit 6 bit 5 bit (4:3) bit 2 bits (1:0) mr1 a mr1 b rx controls rts rxint bit 1 error mode parity mode parity type bits per character 0 = no 1 = yes 0 = rxrdy 1 = ffull 0 = char 1 = block 00 = with parity 01 = force parity 10 = no parity 11 = multidrop mode 0 = even 1 = odd 00 = 5 01 = 6 10 = 7 11 = 8 note: * in block error mode the block error conditions must be cleared by using the error reset command (command 0x40) or a rec eiver reset. mr1 a is accessed when the channel a mr pointer points to mr1. the pointer is set to mr1 by reset or by a `set pointer' command applied via cr command 1. after reading or writing mr1 a, the pointer will point to mr2 a. mr1 a[7] channel a receiver requesttosend control (flow control) this bit controls the deactivation of the rtsn a output (i/o0 b) by the receiver. this output is normally asserted by setting opr[0]b and negated by resetting opr[0]b. mr1 a[7] = 1 causes rtsn a to be negated (i/o0 b is driven to a `1' [v cc ]) upon receipt of a valid start bit if the channel a fifo is full. this is the beginning of the reception of the ninth byte. if the fifo is not read before the start of the tenth byte, an overrun condition will occur and the tenth byte will be lost. however, the bit in opr[0] is not reset and rtsn a will be asserted again when an empty fifo position is available. this feature can be used for flow control to prevent overrun in the receiver by using the rtsn a output signal to control the ctsn input of the transmitting device. mr1[6] receiver interrupt control bit 1. see description under mr0[6]. mr1 a[5] channel a error mode select this bit select the operating mode of the three fifoed status bits (fe, pe, received break) for channel a. in the `character' mode, status is provided on a characterbycharacter basis; the status applies only to the character at the top of the fifo. in the `block' mode, the status provided in the sr for these bits is the accumulation (logicalor) of the status for all characters coming to the top of the fifo since the last `reset error' command for channel a was issued. mr1 a[4:3| channel a parity mode select if `with parity' or `force parity' is selected a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data mr1 a[4:3] = 11 selects channel a to operate in the special multidrop mode described in the operation section. mr1 a[2] channel a parity type select selects the parity type (odd or even) if the a`with parityo mode is programmed by mr1 a[4:3], and the polarity of the forced parity bit if the `force parity' mode is programmed; no effect if `no parity' is programmed. in the special multidrop mode it selects the polarity of the a/d bit. mr1 a[1:0] channel a bits per character select this field selects the number of data bits per character to be transmitted and received. the character length does not include the start, parity, and stop bits. mr2 a is accessed when the channel a mr pointer points to mr2, which occurs after any access to mr1 a. accesses to mr2 a do not change the pointer. mr2 mode register 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr2 a mr2 b channel mode tx controls rts cts enable tx stop bit length note: add 0.5 to binary codes 0 7 for 5 bit character lengths. 00 = normal 01 = autoecho 10 = local loop 11 = remote loop 0 = no 1 = yes 0 = no 1 = yes 0 = 0.563 4 = 0.813 8 = 1.563 c = 1.813 1 = 0.625 5 = 0.875 9 = 1.625 d = 1.875 2 = 0.688 6 = 0.938 a = 1.688 e = 1.938 3 = 0.750 7 = 1.000 b = 1.750 f = 2.000 note: *add 0.5 to values shown for 0 7 if channel is programmed for 5 bits/char. see description in the previous mr2 description
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 44 sr status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sr a sr b received break* framing error* parity error* overrun error txemt txrdy ffull rxrdy 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes note: *these status bits are appended to the corresponding data character in the receive fifo. a read of the status provides th ese bits (7:5) from the top of the fifo together with bits (4:0). these bits are cleared by a areset error statuso command. in character mode they are discarded when the corresponding data character is read from the fifo. in block error mode, the errorreset command (command 4x or receiver reset) must used to clear block error conditions sr a[7] received break channel a received break. this bit indicates that an all zero character of the programmed length has been received without a stop bit. only a single fifo position is occupied when a break is received: further entries to the fifo are inhibited until the rxd a line returns to the marking state for at least onehalf a bit time two successive edges of the internal or external 1x clock. this will usually require a high time of one x1 clock period or 3 x1 edges since the clock of the controller is not synchronous to the x1 clock. when this bit is set, the channel a `change in break' bit in the isr (isr[2]) is set. isr[2] is also set when the end of the break condition, as defined above, is detected. the break detect circuitry can detect breaks that originate in the middle of a received character. however, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. this bit is reset by command 4 (0100) written to the command register or by receiver reset. sr a[6] channel a framing error this bit, when set, indicates that a stop bit was not detected when the corresponding data character in the fifo was received. the stop bit check is made in the middle of the first stop bit position. sr a[5] channel a parity error this bit is set when the `with parity' or `force parity' mode is programmed and the corresponding character in the fifo was received with incorrect parity. in the special multidrop mode the parity error bit stores the receive a/d (address/data) bit. sr a[4] channel a overrun error this bit, when set, indicates that one or more characters in the received data stream have been lost. it is set upon receipt of a new character when the fifo is full and a character is already in the receive shift register waiting for an empty fifo position. when this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. this bit is cleared by a `reset error status' command. sr a[3] channel a transmitter empty (txemt a) this bit will be set when the transmitter under runs, i.e., both the txemt and txrdy bits are set. this bit and txrdy are set when the transmitter is first enabled and at any time it is reenabled after either (a) reset, or (b) the transmitter has assumed the disabled state. it is always set after transmission of the last stop bit of a character if no character is in the thr awaiting transmission. it is reset when the thr is loaded by the cpu, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the under run condition. sr a[2] channel a transmitter ready (txrdy a) this bit, when set, indicates that the transmit fifo is not full and ready to be loaded with another character. this bit is cleared when the transmit fifo is loaded by the cpu and there are (after this load) no more empty locations in the fifo. it is set when a character is transferred to the transmit shift register. txrdy a is reset when the transmitter is disabled and is set when the transmitter is first enabled. characters loaded to the txfifo while this bit is 0 will be lost. this bit has different meaning from isr[0]. sr a[1] channel a fifo full (ffull a) this bit is set when a character is transferred from the receive shift register to the receive fifo and the transfer causes the fifo to become full, i.e., all eight fifo positions are occupied. it is reset when the cpu reads the receive fifo. if a character is waiting in the receive shift register because the fifo is full, ffull a will not be reset when the cpu reads the receive fifo. this bit has different meaning from isr1 when mr1 6 is programmed to a `1'. sr a[0] channel a receiver ready (rxrdy a) this bit indicates that a character has been received and is waiting in the fifo to be read by the cpu. it is set when the character is transferred from the receive shift register to the fifo and reset when the cpu reads the receive fifo, only if (after this read) there are no more characters in the fifo. sr b channel b status register the bit definitions for this register are identical to the bit definitions for sr a, except that all status applies to the channel b receiver and transmitter and the corresponding inputs and outputs.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 45 csr a channel a clock select register csr a [7:4] channel a receiver clock select this field selects the baud rate clock for the channel a receiver. the field definition is shown in table 13. csr clock select register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csr a & csr b receiver clock select transmitter clock select see text and table 13 see text and table 13 table 13. baud rate (base on a 14.7456 mhz crystal clock) mr0[0] = 0 (normal mode) mr0[0] = 1 (extended mode i) mr0[2] = 1 (extended mode ii) csr a [7:4] acr[7] = 0 acr[7] = 1 acr[7] = 0 acr[7] = 1 acr[7] = 0 acr[7] = 1 0000 50 75 300 450 4,800 7,200 0001 110 110 110 110 880 880 0010 134.5 134.5 134.5 134.5 1,076 1,076 0011 200 150 1200 900 19.2k 14.4k 0100 300 300 1800 1800 28.8k 28.8k 0101 600 600 3600 3600 57.6k 57.6k 0110 1,200 1,200 7200 7,200 115.2k 115.2k 0111 1,050 2,000 1,050 2,000 1,050 2,000 1000 2,400 2,400 14.4k 14.4k 57.6k 57.6k 1001 4,800 4,800 28.8k 28.8k 4,800 4,800 1010 7,200 1,800 7,200 1,800 57.6k 14.4k 1011 9,600 9,600 57.6k 57.6k 9,600 9,600 1100 38.4k 19.2k 230.4k 115.2k 38.4k 19.2k 1101 timer timer timer timer timer timer 1110 i/o4 a16x i/o4 a16x i/o4 a16x i/o4 a16x i/o4 a16x i/o4 a16x 1111 i/o4 a1x i/o4 a1x i/o4 a1x i/o4 a1x i/o4 a1x i/o4 a1x note: the receiver clock is always a 16x clock except for csr a [7:4] = 1111. csr a [3:0] channel a external transmitter clock select this field selects the baud rate clock for the channel a transmitter. the field definition is as shown in table 13, except as follows: csr a [3:0] acr[7] = 0 acr[7] = 1 1110 i/o3 a16x i/o3 a16x 1111 i/o3 a1x i/o3 a1x the transmitter clock is always a 16x clock except for csr[3:0] = 1111. csr b [7:4] channel b receiver clock select this field selects the baud rate clock for the channel b receiver. the field definition is as shown in table 13, except as follows: csr b [7:4] acr[7] = 0 acr[7] = 1 1110 i/o6 a16x i/o6 a16x 111 i/o6 a1x i/o6 a1x the receiver clock is always a 16x clock except for csr b [7:4] = 1111. csr b [3:0] channel b transmitter clock select this field selects the baud rate clock for the channel b transmitter. the field definition is as shown in table 13, except as follows: csr b [3:0] acr[7] = 0 acr[7] = 1 1110 i/o5 a16x i/o5 a16x 1111 i/o5 a1x i/o5 a1x the transmitter clock is always a 16x clock except for csr b [3:0] = 1111. rx fifo register. for characters shorter than 8 bits the unused bits are set to zero bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits of the received data characters. tx fifo register. for characters shorter than 8 bits the unused bits are set to zero bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits of the data characters to be transmitted cr a and b command register cr, one for each channel, controls the channel commands and enables/disables the receiver and transmitter. commands may be to the upper and lower four bits in the same bus cycle. if both enable and disable bits are set to 1 in the lower four bits a disable will result.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 46 cr command register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cr a &cr b miscellaneous commands disable tx enable tx disable rx enable rx see text of channel command register 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no note: access to the miscellaneous commands should be separated by 3 x1 clock edges. a disabled transmitter cannot be loaded. command register table a and b commands 0xe, 0xf (marked with *) are global and exist only in channel a's register space. channel command code channel command channel command code channel command cr[7:4] description cr[7:4] description 0000 nop 1000 assert rtsn (i/o0 b or i/o1 b) 0001 set mr pointer to 1 1001 negate rtsn (i/o0 b or i/o1 b) 0010 reset receiver 1010 set c/t receiver timeout mode on 0011 reset transmitter 1011 set mr pointer to 0 0100 reset error status 1100 set c/t receiver timeout mode off 0101 reset break change interrupt 1101 block error status on rxfifo load 0110 begin transmit break 1110 ? power down mode on 0111 end transmit break 1111 ? disable power down mode ? 0000 no command. ? 0001 set mr pointer to 1 ? 0010 reset receiver. immediately resets the receiver as if hardware reset had been applied. the receiver is reset and the fifo pointer is reset to the first location effectively discarding all unread characters in the fifo. ? 0011 reset transmitter. immediately resets the transmitter as if a hardware reset had been applied. the transmitter is reset and the fifo pointer is reset to the first location effectively discarding all untransmitted characters in the fifo. ? 0100 reset error status. clears the received break, parity error, framing error, and overrun error bits in the status register (sr[7:4]). i it is used in either character or block mode. in block mode it would normally be used after the block is read. ? 0101 reset break change interrupt. causes the break detect change bit in the interrupt status register (isr[2]) to be cleared to zero. ? 0110 start break. forces the txd output low (spacing). if the transmitter is empty, the start of the break condition will be delayed up to two bit times. if the transmitter is active and the txfifo is empty then the break begins when transmission of the current character is completed. if there are characters in the txfifo, the start of break is delayed until all characters presently in the txfifo and any subsequent characters loaded have been transmitted. (tx idle must be true before break begins). the transmitter must be enabled to start a break. ? 0111 stop break. the txd line will go high (marking) within two bit times. txd will remain high for one bit time before the next character is transmitted. ? 1000 assert rtsn. causes the rtsn output to be asserted (low). ? 1001 negate rtsn. causes the rtsn output to be negated (high). note : the two commands above actually reset and set, respectively, the i/o0 b or i/o1 b pin associated with the opr register. ? 1010 set c/t receiver time out mode on. the receiver in this channel will restart the c/t as reach receive character is transferred from the shift register to the rxfifo. the c/t is placed in the counter mode, the start/stop counter commands are disabled, the counter is stopped and the counter ready bit, isr(3), is reset. ? 1011 set mr pointer to 0 ? 1100 set c/t receiver time out mode off ? 1101 block error status accumulation on fifo entry. allows the areceived breako, aframing erroro and aparity erroro bits to be set as the received character is loaded to the rxfifo. (normally these bits are set on reading of the data from the rxfifo) setting this mode can give information about error data up to 256 bytes earlier than the normal mode. however it clouds the ability to know precisely which byte(s) are in error. ? 1110 power down mode on ? 1111 disable power down mode
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 47 ipcr input port configuration register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ipcr delta i/o 3a delta i/o 2a delta i/o 1a delta i/o 0a i/o 3a i/o 2a i/o 1a i/o 0a 0 = no change 1 = change 0 = no change 1 = change 0 = no change 1 = change 0 = no change 1 = change 0 = low 1 = high 0 = low 1 = high 0 = low 1 = high 0 = low 1 = high ipcr [7:4] i/03a, i/o2 a, i/o1 a, i/o0 a changeofstate these bits are set when a changeofstate, as defined in the input port section of this data sheet, occurs at the respective input pins. they are cleared when the ipcr is read by the cpu. a read of the ipcr also clears isr [7], the input change bit in the interrupt status register. the setting of these bits can be programmed to generate an interrupt to the cpu. ipcr [3:0] i/o3 a, i/o2 a, i/o1 a, i/o0 a logical level of i/o pin. these bits provide the current state of the respective inputs. the information is unlatched and reflects the state of the input pins at the time the ipcr is read. acr auxiliary control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acr brg set select counter timer mode and clock source select delta i/o3 a interrupt enable delta i/o2 a interrupt enable delta i/o1 a interrupt enable delta i/o0 a interrupt enable 0 = set 1 1 = set 2 see table 14 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled acr[7] baud rate generator set select this bit selects one of two sets of baud rates to be generated by the brg and it effects both channels. (see table 13). acr[6:4] counter/timer mode and clock source select this field selects the operating mode of the counter/timer and its clock source as shown in table 14. acr [3:0] i/o3 a, i/o2 a, i/o1 a, i/o0 a changeofstate interrupt enable this field selects which bits of the input port change register (ipcr) cause the input change bit in the interrupt status register (isr [7]) to be set. if a bit is in the `on' state the setting of the corresponding bit in the ipcr will also result in the setting of isr [7], which results in the generation of an interrupt output if imr [7] = 1. if a bit is in the `off' state, the setting of that bit in the ipcr has no effect on isr [7]. table 14. acr 6:4 field definition acr(6:4) mode clock source 000 counter external (i/02a) 001 counter txc a 1x clock of channel a transmitter 010 counter txc b 1x clock of channel b transmitter 011 counter (x1/sclk) clock divided by 16 100 timer external (i/o 2a) 101 timer external (i/o2 a) divided by 16 110 timer crystal or external clock (x1/sclk) 111 timer (x1/sclk) clock divided by 16 note: the timer mode generates a square wave.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 48 isr interrupt status register this register provides the status of all potential interrupt sources. the contents of this register are masked by the interrupt mask register (imr). if a bit in the isr is a `1' and the corresponding bit in the imr is also a `1' then intrn output will be asserted (low). if the corresponding bit in the imr is a zero the state of the bit in the isr has no effect on the intrn output. note that the imr does not mask the reading of the isr the true status will be provided regardless of the contents of the imr. the contents of this register are initialized to h`00' when the duart is reset. isr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffull b txrdy b counter ready delta break a rxrdy/ ffull a txrdy a 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled isr[7] input port change status this bit is a `1' when a changeofstate has occurred at the i/o(3:0)a or b inputs and that event has been selected to cause an interrupt by the programming of acr[3:0]. the bit is cleared when the cpu reads the ipcr. isr[6] channel b change in break this bit, when set, indicates that the channel b receiver has detected the beginning or the end of a received break. it is reset when the cpu issues a channel b `reset break change interrupt' command. isr[5] rx b interrupt this bit indicates that the channel b receiver is interrupting according to the fill level programmed by the mr0 and mr1 registers. this bit has a different meaning than the receiver ready/full bit in the status register. isr[4] tx b interrupt this bit indicates that the channel b transmitter is interrupting according to the interrupt level programmed in the mr0[5:4] bits. this bit has a different meaning than the tx rdy bit in the status register. isr[3] counter ready. in the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. in the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches zero count). the bit is reset by a stop counter command. the command, however, does not stop the counter/timer. isr[2] channel a change in break this bit, when set, indicates that the channel a receiver has detected the beginning or the end of a received break. it is reset when the cpu issues a channel a `reset break change interrupt' command. isr[1] rx a interrupt this bit indicates that the channel a receiver is interrupting according to the fill level programmed by the mr0 and mr1 registers. this bit has a different meaning than the receiver ready/full bit in the status register. isr[0] tx a interrupt this bit indicates that the channel a transmitter is interrupting according to the interrupt level programmed in the mr0[5:4] bits. this bit has a different meaning than the tx rdy bit in the status register. imr interrupt mask register the programming of this register selects which bits in the isr causes an interrupt output. if a bit in the isr is a `1' and the corresponding bit in the imr is also a `1' the intrn output will be asserted. if the corresponding bit in the imr is a zero, the state of the bit in the isr has no effect on the intrn output. note that the imr does not mask the programmable interrupt outputs i/o3 bi/o7 b or the reading of the isr. imr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffull b txrdy b counter ready delta break a rxrdy/ ffull a txrdy a 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled 0=not enabled 1=enabled ctpu counter timer preset upper (counter/timer 0) cptu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the upper eight (8) bits for the 16 bit counter timer preset register ctpl counter timer preset lower (counter/timer 0) ctpl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the lower eight (8) bits for the 16 bit counter timer preset register ctvu counter timer value upper (counter/timer 0) cpvl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the lower eight (8) bits for the 16 bit counter timer value
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 49 ctvl counter timer value lower (counter/timer 0) ctvl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the lower eight (8) bits for the 16 bit counter timer value register only the counter/timer 0 is available in the low order 16position address map. issuing the start command loads the c/t with the preset value. the stop command resets the c/t ready bit in the isr (interrupt status register) and captures the c/t value in the output latches of the c/t. in the special time out mode the start and stop commands are ignored. the astart command is executed by a read at address 0xe; the stop at 0xf. ivr interrupt vector register in 68k mode and general purpose read write register in the x86 mode ivr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the eight (8) bits of the interrupt vector in the 68k mode. ipr input port register i/o(6:0) a ipr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 logical levels or the i/o[6:0] a, bit 7 read as a1o opcr output port configuration register. controls [7:2] b bit 7 bit 6 bit 5 bit 4 bit (3:2) bit (1:0) i/o7 b i/o6 b i/o5 b i/o4 b i/o3 b i/o2 b 0 = opr[7] 1 = tx rdy b 0 = opr[6] 1 = tx rdy a 0 = opr[5] 1 = rx rdy / ffull b 0 = opr[4] 1 = rx rdy / ffull a 00 = opr[3] 01 = c/t output 10 = txc b(1x) 11 = rxc b(1x) 00 = opr[2] 01 = txc a(16x) 10 = txc a(1x) 11 = rxc a(1x) note : i/o0 b and i/o1 b output opr(0) and opr(1) respectively. under program control of mr1 and mr2 the signals rtsn a for i/o0 b and rtsn b for i/o1 b may be assigned. opcr[7] this bit programs the i/o7 b output to provide one of the following: ? 0 the complement of opr[7]. ? 1 the channel b transmitter interrupt output which is the complement of isr[4]. when in this mode i/o7 acts as an open drain output. note that this output is not masked by the contents of the imr. opcr[6] this bit programs the i/o6 b output to provide one of the following: ? 0 the complement of opr[6]. ? 1 the channel a transmitter interrupt output which is the complement of isr[0]. when in this mode i/o6 acts as an open drain output. note that this output is not masked by the contents of the imr. opcr[5] this bit programs the i/o5 b output to provide one of the following: ? 0 the complement of opr[5]. ? 1 the channel b receiver interrupt output which is the complement of isr[5]. when in this mode i/o5 acts as an opendrain output. note that this output is not masked by the contents of the imr. opcr[4] this field programs the i/o4 b output to provide one of the following: ? 0 the complement of opr[4]. ? 1 the channel a receiver interrupt output which is the complement of isr[1]. when in this mode i/o4 acts as an opendrain output. note that this output is not masked by the contents of the imr. opcr[3:2] this bit programs the i/o3 b output to provide one of the following: ? 00 the complement of opr[3]. ? 01 the counter/timer output, in which case i/o3 acts as an opendrain output. in the timer mode, this output is a square wave at the programmed frequency. in the counter mode, the output remains high until terminal count is reached, at which time it goes low. the output returns to the high state when the counter is stopped by a stop counter command. note that this output is not masked by the contents of the imr. ? 10 the 1x clock for the channel b transmitter that shifts the transmitted data. if data is not being transmitted, a free running 1x clock is output. ? 11 the 1x clock for the channel b receiver that samples the received data. if data is not being received, a free running 1x clock is output. opcr[1:0] this field programs the i/o2 b output to provide one of the following: ? 00 the complement of opr[2]. ? 01 the 16x clock for the channel a transmitter. this is the clock selected by csr a [3:0], and will be a 1x clock if csr a [3:0] = 1111. ? 10 the 1x clock for the channel a transmitter that shifts the transmitted data. if data is not being transmitted, a free running 1x clock is output. ? 11 the 1x clock for the channel a receiver that samples the received data. if data is not being received, a free running 1x clock is output.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 50 sopr set bits in the opr ones in the byte written to this register will cause the corresponding bit positions in the opr to set to 1. zeros have no effe ct. this allows software to set individual bits without keeping a copy of the opr bit configuration. set opr bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o7 b i/o6 b i/o5 b i/o4 b i/o3 b i/o2 b i/o1 b i/o0 b 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change 1=set bit 0=no change ropr reset bits in the opr ones in the byte written to the ropr will cause the corresponding bit positions in the opr to set to 0. zeros have no effect. t his allows software to reset individual bits with our keeping a copy of the opr bit configuration. reset opr bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o7 b i/o6 b i/o5 b i/o4 b i/o3 b i/o2 b i/o1 b i/o0 b 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change 1=reset bit 0=no change opr output port register the bits in the opr register are controlled by the use of the sopr and ropr commands. the output pins (op pins) drive the compl iment of the data stored in this register. opr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o7 b i/o6 b i/o5 b i/o4 b i/o3 b i/o2 b i/o1 b i/o0 b 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low 0=pin high 1=pin low
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 51 register maps the registers of the sc28l202 are loosely partitioned into two groups: those used in controlling data channels and those used in handling the actual data flow and status. below is shown the general configuration of all the register addressed. the oregister map summaryo shows the configuration of the lower four bits of the address that is the same for the individual uarts. it also shows the addresses for the several in the address space of uart a and uart b that apply to the total chip configuration. the oregister map detailo shows the use of every address in the 8bit address space. register map detail (based on 28l92) register map note: the register maps for channels a and b (uarts a and b) contain some control registers that configure the entire chip. these are denoted by a oo symbol addressing scheme: a b+8 default extension +16 note: addresses 0x00 to 0x0f represent the ac92 registero map a(6:0) read write default 000 0000 (0x00) mode register (mr0 a, mr1 a, mr2 a) default mode register (mr0 a, mr1 a, mr2 a) default 000 0001 (0x01) status register (sr a) clock select register (csr a) default 000 0010 (0x02) command register (cr a) default 000 0011 (0x03) receiver fifo register (rxfifo a) transmitter fifo register (txfifo a) 000 0100 (0x04) ? input port change register (ipcr) default ? auxiliary control register (acr) default 000 0101 (0x05) ? interrupt status register (isr) default ? interrupt mask register (imr) default 000 0110 (0x06) ? counter timer value register upper (ctvu 0) ? counter timer preset register upper (ctpu 0) 000 0111 (0x07) ? counter timer value register lower (ctvl 0) ? counter timer preset register lower (ctpl 0) 000 1000 (0x08) mode register (mr0 b, mr1 b, mr2 b) default mode register (mr0 b, mr1 b, mr2 b) default 000 1001 (0x09) status register (sr b) clock select register (csr b) default 000 1010 (0x0a) command register (cr b) default 000 1011 (0x0b) receiver fifo register (rxfifo b) transmitter fifo register (txfifo b) 000 1100 (0x0c) ? interrupt vector register (ivr) global ? interrupt vector register (ivr) global 000 1101 (0x0d) ? input port register (ipr) i/o(6:0) a ? output port configuration register (opcr) i/o(7:2)b 000 1110 (0x0e) ? start counter command default c/t 0 ? set output port register (sopr) i/o(7:0)b 000 1111 (0x0f) ? stop counter command default c/t 0 ? reset output port register (ropr) i/o(7:0)b extension 001 0000 (0x10) receiver fifo fill level (rxfl a) ? set output port register (sopr a) 001 0001 (0x11) transmitter fifo empty level (txel a) ? reset output port register (ropr a) 001 0010 (0x12) ? enhanced operation status (eos) command register extension (crx a) 001 0011 (0x13) ? input port change register upper (ipcru a) ? i/o port configuration register 0 (i/opcr 0) 001 0100 (0x14) ? input port change register lower (ipcrl a) ? i/o port configuration register 1 (i/opcr 1) 001 0101 (0x15) ? input port register (ipr a) 001 0110 (0x16) ? counter timer value register upper (ctvu 0) ? counter timer preset register upper (ctpu 0) 001 0111 (0x17) ? counter timer value register lower (ctvl 0) ? counter timer preset register lower (ctpl 0) 001 1000 (0x18) receiver fifo fill level (rxfl b) ? set output port register (sopr b) 001 1001 (0x19) transmitter fifo empty level (txel b) ? reset output port register (ropr b) 001 1010 (0x1a) command register extension (crx b) 001 1011 (0x1b) ? input port change register upper (ipcru b) ? i/o port configuration register 2 (i/opcr 2) 001 1100 (0x1c) ? input port change register lower (ipcrl b) ? i/o port configuration register 3 (i/opcr 3) 001 1101 (0x1d) ? input port register (ipr b) 001 1110 (0x1e) ? counter timer value register upper (ctvu 1) ? counter timer preset register upper (ctpu 1) 001 1111 (0x1f) ? counter timer value register lower (ctvl 1) ? counter timer preset register lower (ctpl 1)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 52 register map (based on 28l92) note: the register maps for channels a and b (uarts a and b) contain some control registers that configure the entire chip. these are denoted by a o ? o symbol a(6:0) read write extension 010 0000 (0x20) mode register 0 (mr0 a) new address mode register 0 (mr0 a) new address 010 0001 (0x21) mode register 1 (mr1 a) new address mode register 1 (mr1 a) new address 010 0010 (0x22) mode register 2 (mr2 a) new address mode register 2 (mr2 a) new address 010 0011 (0x23) mode register 3 (mr3 a) new address mode register 3 (mr3 a) new address 010 0100 (0x24) ? counter/timer clock source (ctcs 0) ? counter/timer clock source (ctcs 0) 010 0101 (0x25) interrupt status register (isr a) ? interrupt mask register (imr a) 010 0110 (0x26) ? programmable brg preset lower (pbrgpl 0) ? programmable brg preset lower (pbrgpl 0) 010 0111 (0x27) ? programmable brg preset upper (pbrgpu 0) ? programmable brg preset upper (pbrgpu 0) 010 1000 (0x28) mode register 0 (mr0 b) new address mode register 0 (mr0 b) new address 010 1001 (0x29) mode register 1 (mr1 b) new address mode register 1 (mr1 b) new address 010 1010 (0x2a) mode register 2 (mr2 b) new address mode register 2 (mr2 b) new address 010 1011 (0x2b) mode register 3 (mr3 b) new address mode register 3 (mr3 b) new address 010 1100 (0x2c) ? counter/timer clock source (ctcs 1) ? counter/timer clock source (ctcs 1) 010 1101 (0x2d) ? interrupt status register (isr b) ? interrupt mask register (imr b) 010 1110 (0x2e) 010 1111 (0x2f) 011 0000 (0x30) receiver clock select register (rxcsr a) receiver clock select register (rxcsr a) 011 0001 (0x31) transmitter clock select register (txcsr a) transmitter clock select register (txcsr a) 011 0010 (0x32) ? input port change interrupt enable (ipce a) ? input port change interrupt enable (ipce a) 011 0011 (0x33) ? programmable brg clock source (pbrgcs) ? programmable brg clock source (pbrgcs) 011 0100 (0x34) 011 0101 (0x35) 011 0110 (0x36) ? programmable brg preset lower (pbrgpl 1) ? programmable brg preset lower (pbrgpl 1) 011 0111 (0x37) ? programmable brg preset upper (pbrgpu 1) ? programmable brg preset upper (pbrgpu 1) 011 1000 (0x38) receiver clock select register (rxcsr b) receiver clock select register (rxcsr b) 011 1001 (0x39) transmitter clock select register (txcsr b) transmitter clock select register (txcsr b) 011 1010 (0x3a) ? input port change interrupt enable (ipce b) ? input port change interrupt enable (ipce b) 011 1011 (0x3b) 011 1100 (0x3c) 011 1101 (0x3d) 011 1110 (0x3e) 011 1111 (0x3f)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 53 register map (based on 28l92) note: the register maps for channels a and b (uarts a and b) contain some control registers that configure the entire chip. these are denoted by a o ? o symbol a(6:0) read write new 100 0000 (0x40) system enable status (ses a) watchdog, character and x enable(wcxer a) 100 0001 (0x41) xon character register (xoncr a) xon character register (xoncr a) 100 0010 (0x42) xoff character register (xoffcr a) xoff character register (xoffcr a) 100 0011 (0x43) address recognition character (arcr a) address recognition character (arcr a) 100 0100 (0x44) xon/xoff interrupt status register (xisr a) 100 0101 (0x45) special function register (sfr a) special function register (sfr a) 100 0110 (0x46) receiver fifo interrupt level (rxfil a) receiver fifo interrupt level (rxfil a) 100 0111 (0x47) transmitter fifo interrupt level (txfil a) transmitter fifo interrupt level (txfil a) 100 1000 (0x48) system enable status (ses b) watchdog, character and x enable (wcxer b) 100 1001 (0x49) xon character register (xoncr b) xon character register (xoncr b) 100 1010 (0x4a) xoff character register (xoffcr b) xoff character register (xoffcr b) 100 1011 (0x4b) address recognition character (arcr b) address recognition character (arcr b) 100 1100 (0x4c) xon/xoff interrupt status register (xisr b) 100 1101 (0x4d) special function register (sfr b) special function register (sfr b) 100 1110 (0x4e) receiver fifo interrupt level (rxfil b) receiver fifo interrupt level (rxfil b) 100 1111 (0x4f) transmitter fifo interrupt level (txfil b) transmitter fifo interrupt level (txfil b) 101 0000 (0x50) bidding control register break change (bcrbrk a) bidding control register break change (bcrbrk a) 101 0001 (0x51) bidding control register change of state (bcrcos a) bidding control register change of state (bcrcos a) 101 0010 (0x52) bidding control register counter/timer (bcrct a) bidding control register counter/timer (bcrct a) 101 0011 (0x53) bidding control register xon (bcrx a) bidding control register xon (bcrx a) 101 0100 (0x54) bidding control register address (bcra a) bidding control register address (bcra a) 101 0101 (0x55) bidding control register loop back error (bcrlbe a) bidding control register loop back error (bcrlbe a) 101 0110 (0x56) 101 0111 (0x57) 101 1000 (0x58) bidding control register break change (bcrbrk b) bidding control register break change (bcrbrk b) 101 1001 (0x59) bidding control register change of state (bcrcos b) bidding control register change of state (bcrcos b) 101 1010 (0x5a) bidding control register counter/timer (bcrct b) bidding control register counter/timer (bcrct b) 101 1011 (0x5b) bidding control register xon (bcrx b) bidding control register xon (bcrx b) 101 1100 (0x5c) bidding control register address (bcra b) bidding control register address (bcra b) 101 1101 (0x5d) bidding control register loop back error (bcrlbe b) bidding control register loop back error (bcrlbe b) 101 1110 (0x5e) 101 1111 (0x5f)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 54 register map (based on 28l92) note: the register maps for channels a and b (uarts a and b) contain some control registers that configure the entire chip. these are denoted by a o ? o symbol a(6:0) read write global 110 0000 (0x60) ? interrupt control register (icr) ? interrupt control register (icr) 110 0001 (0x61) ? current interrupt register (cir) ? update current interrupt register (ucir) 110 0010 (0x62) 110 0011 (0x63) 110 0100 (0x64) ? interrupt vector register (ivr) ? interrupt vector register (ivr) 110 0101 (0x65) 110 0110 (0x66) ? global chip configuration register (gccr) ? global chip configuration register (gccr) 110 0111 (0x67) ? test & revision register (trr) ? test & revision register (trr) 110 1000 (0x68) 110 1001 (0x69) 110 1010 (0x6a) 110 1011 (0x6b) 110 1100 (0x6c) 110 1101 (0x6d) 110 1110 (0x6e) 110 1111 (0x6f) 111 0000 (0x70) ? global interrupt channel register (gicr) 111 0001 (0x71) ? global interrupt byte count register (gibcr) 111 0010 (0x72) ? global interrupt type register (gitr) 111 0011 (0x73) ? global rxfifo register (grxfifo) ? global txfifo register (gtxfifo) 111 0100 (0x74) 111 0101 (0x75) 111 0110 (0x76) 111 0111 (0x77) ? scan test control register (stcr) ? scan test control register (stcr) 111 1000 (0x78) 111 1001 (0x79) 111 1010 (0x7a) 111 1011 (0x7b) 111 1100 (0x7c) 111 1101 (0x7d) 111 1110 (0x7e) 111 1111 (0x7f)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 55 absolute maximum ratings 1 symbol parameter rating unit t amb operating ambient temperature range 2 note 4 c t stg storage temperature range 65 to +150 c v cc voltage from v cc to gnd 3 0.5 to +7.0 0.5 to +7.0 v v ss voltage from any pin to gnd 3 0.5 to v cc +0.5 v p power dissipation (plcc44) 2.4 w p power dissipation (pqfp44) 1.78 w derating factor above 25 c (plcc44) 19 mw/ c derating factor above 25 c (pqfp44) 15 mw/ c notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this speci fication is not implied. 2. for operating at elevated temperatures, the device must be derated based on + 150 c maximum junction temperature. 3. this product includes circuitry specifically designed for the protection of its internal devices from damaging effects of exc essive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rate d maxima. 4. parameters are valid over specified temperature range.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 56 dc electrical characteristics 123 (nominal 5 volts) vcc = 5v 10% ta = 40 to +85 c unless otherwise specified limits unit symbol parameter test conditions min typ max v il input low voltage 1.2 0.8 v v ih v ih input high voltage (except x1/clk) 40 to +85 c 2.4 1.5 v v ih input high voltage (x1/clk) 0.8*vcc 2.4 v v ol output low voltage i ol = 4 ma 0.2 0.4 v v oh output high voltage (except od outputs) 4 i oh = 400 ua vcc 0.5 v i ix1pd x1/clk input current power down v in = 0 to v cc 0.5 0.05 0.5 m a i ilx1 x1/clk input low current operating v in = 0 130 0 m a i ihx1 x1/clk input high current operating v in = v cc 0 130 m a in p ut leakage current: ii inp u t leakage c u rrent : all exce p tin p ut p ort p ins in p ut p ort p ins 5 v in = 0 to v cc 0.5 0.05 +0.5 m a all exce t in ut ort ins in ut ort ins v in = 0 to v cc 8 0.05 +0.5 m a i ozh output off current high, 3state data bus v in = v cc 0.5 m a i ozl output off current low, 3state data bus v in = 0v 0.5 m a i odl opendrain output low current in offstate v in = 0 0.5 m a i odh opendrain output high current in offstate v in = v cc 0.5 m a power supply current: 6 i cc operating mode cmos input levels 25 ma power down mode 7 cmos input levels 1 5 m a notes: 1. parameters are valid over specified temperature range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4v and 3.0v with a transitio n time of 5 ns maximum. for x1/clk this swing is between 0.4v and 4.4v. all time measurements are referenced at input voltages of 0.8v and 2.0 v and output voltages of 0.8v and 2.0v, as appropriate. 3. typical values are at +25 c, typical supply voltages, and typical processing parameters. 4. test conditions for outputs: c l = 150 pf, except interrupt outputs. test conditions for interrupt outputs: c l = 50 pf, r l = 2.7k ohm to v cc . 5. input port pins have active pull up transistors that will source a typical 2 m a from vcc when the input pins are at vss. input port pins at v cc source 0.0 m a 6. all outputs are disconnected. inputs are switching between cmos levels of v cc 0.2v and v ss + 0.2v. 7. see uart application note for power down currents of 10 ua or less.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 57 ac characteristics 1,2,3 (nominal 5 volts) vcc = 5v 10% ta = 40 to +85 c unless otherwise specified limits 4 symbol parameter min typ max unit reset timing (see figure 3) t res reset pulse width 100 18 ns bus timing 5 (see figure ___) t *as a6a0 setup time to rdn, wrn low 10 6 ns t *ah a6a0 hold time from rdn, wrn low 20 ns t *cs cen setup time to rdn, wrn low 0 ns t *ch cen hold time from rdn. wrn hi 0 ns t *rw wrn, rdn pulse width (low time) 15 11 ns t *dd data valid after rdn low (125 pf load) see loading table for smaller loads 15 40 ns t *da rdn low to data bus active 6 0 ns t *df data bus floating after rdn or cen high 20 ns t *di rdn or cen high to data bus invalid 7 0 ns t *ds data bus setup time before wrn or cen high (write cycle) 25 17 ns t *dh data hold time after wrn high 0 15 ns t *rwd high time between read and/or write cycles 5,7 15 12 ns port timing 5 (see figure 7) t *ps port in setup time before rdn low (read ip ports cycle) 0 20 ns t *ph port in hold time after rdn high 0 20 ns t *pd op port valid after wrn or cen high (opr write cycle) 40 60 ns interrupt timing (see figure 8) intrn (or i/o(7:3)b when used as interrupts) negated from: read rxfifo (rxrdy/ffull interrupt) 40 60 ns write txfifo (txrdy interrupt) 40 60 ns t *ir reset command (delta break change interrupt) 40 60 ns stop c/t command (counter/timer interrupt 40 60 ns read ipcr (delta input port change interrupt) 40 60 ns write imr (clear of change interrupt mask bit(s)) 40 60 ns clock timing (see figure 9) t *clk x1/clk high or low time 30 20 ns f *clk x1/clk frequency (7.0 to 16.2 mhz with crystal) 1.0 14.7 50 mhz f *ctc c/t clk (ip2) high or low time (c/t external clock input) 30 20 ns f *ctc c/t clk (ip2) frequency 8 0 mhz t *rx rxc high or low time (16x) 30 ns f *rx rxc frequency (16x) 0 50 mhz rxc frequency (1x) 8,9 0 3 mhz t *tx txc high or low time (16x) 30 ns f *tx txc frequency (16x) 50 mhz txc frequency (1x) 8,9 0 3 mhz transmitter timing (see figure 12) t *txd txd output delay from txc low (txc input pin) 40 60 ns t *tcs output delay from txc output pin low to txd data output 6 30 ns receiver timing (see figure 13) t *rxs rxd data setup time to rxc high 50 40 ns t *rxh rxd data hold time from rxc high 50 40 ns 68000 or motorola bus timing (see figure ___) t dcr dackn low (read cycle) from x1 high 15 20 ns t dcw dackn low (write cycle) from x1 high 15 20 ns t dah dackn high from csn or iackn high 8 10 ns t dat dackn high impedance from csn or iackn high 8 10 ns t csc csn or iackn setup time to x1 high for minimum dackn cycle 10 8 ns
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 58 notes: 1. parameters are valid over specified temperature range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4v and 3.0v with a transitio n time of 5 ns maximum. for x1/clk this swing is between 0.4v and 4.4v. all time measurements are referenced at input voltages of 0.8v and 2.0 v and output voltages of 0.8v and 2.0v, as appropriate. 3. test conditions for outputs: c l = 150 pf, except interrupt outputs. test conditions for interrupt outputs: c l = 50 pf, r l = 2.7k ohm to v cc . 4. typical values are at +25 c, typical supply voltages, and typical processing parameters. 5. timing is illustrated and referenced to the wrn and rdn inputs. also, cen may be the `strobing' input. cen and rdn (also cen and wrn) are ored internally. the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. guaranteed by characterization of sample units. 7. if cen is used as the `strobing' input, the parameter defines the minimum high times between one cen and the next. the rdn si gnal must be negated for t rwd time to guarantee that any status register changes are valid. 8. minimum frequencies are not tested but are guaranteed by design. 9. clocks for 1x mode should be symmetrical.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 59 dc electrical characteristics 1,2,3 (nominal 3.3 volts) vcc = 3.3v 10% ta = 40 to +85 c unless otherwise specified limits unit symbol parameter test conditions min typ max v il input low voltage 0.65 0.2*vcc v v ih input high voltage (x1/clk) 0.8*vcc 1.7 v v ol output low voltage i ol = 4 ma 0.2 0.4 v v oh output high voltage (except od outputs) 4 i oh = 400 ua vcc0.5 vcc0.2 v i ix1pd x1/clk input current power down v in = 0 to v cc 0.5 0.05 +0.5 m a i ilx1 x1/clk input low current operating v in = 0 80 0 m a i ihx1 x1/clk input high current operating v in = v cc 0 80 m a i i input leakage current: all except input port pins input port pins 5 v in = 0 to v cc 0.5 0.05 +0.5 m a v in = 0 to v cc 8 0.5 +0.5 m a i ozh output off current high, 3state data bus v in = v cc 0.5 m a i ozl output off current low, 3state data bus v in = 0v 0.5 m a i odl opendrain output low current in offstate v in = 0 0.5 m a i odh opendrain output high current in offstate v in = v cc 0.5 m a i cc power supply current: 6 operating mode cmos input levels 25 ma power down mode 7 cmos input levels 1 5.0 m a notes: 1. parameters are valid over specified temperature range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4v and 3.0v with a transitio n time of 5 ns maximum. for x1/clk this swing is between 0.4v and 4.4v. all time measurements are referenced at input voltages of 0.8v and 2.0 v and output voltages of 0.8v and 2.0v, as appropriate. 3. typical values are at +25 c, typical supply voltages, and typical processing parameters. 4. test conditions for outputs: c l = 150 pf, except interrupt outputs. test conditions for interrupt outputs: c l = 50 pf, r l = 2.7k ohm to v cc . 5. input port pins have active pull up transistors that will source a typical 2 m a from vcc when the input pins are at vss. input port pins at vcc source 0.0 m a 6. all outputs are disconnected. inputs are switching between cmos levels of v cc 0.2v and v ss + 0.2v. 7. see uart application note for power down currents of 10 ua or less.
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 60 ac characteristics 1,2,3 (nominal 3.3 volts) vcc = 3.3v 10% ta = 40 to +85 c unless otherwise specified limits 4 symbol parameter min typ max unit reset timing (see figure 3) t res reset pulse width 100 18 ns bus timing (see figure ___) t *as a6a0 setup time to rdn, wrn low 10 6 ns t *ah a6a0 hold time from rdn, wrn low 25 15 ns t *cs cen setup time to rdn, wrn low 0 ns t *ch cen hold time from rdn. wrn hi 0 ns t *rw wrn, rdn pulse width (low time) 20 15 ns t *dd data valid after rdn low (125 pf load) see load table for smaller loads 20 50 ns t *da rdn low to data bus active 0 ns t *df data bus floating after rdn or cen high 15 25 ns t *di rdn or cen high to data bus invalid 0 ns t *ds data bus setup time before wrn or cen high (write cycle) 25 20 ns t *dh data hold time after wrn high 0 15 ns t *rwd high time between read and/or write cycles 20 14 ns port timing (see figure 7) t *ps port in setup time before rdn low (read ip ports cycle) 0 20 ns t *ph port in hold time after rdn high 0 20 ns t *pd op port valid after wrn or cen high (opr write cycle) 50 70 ns interrupt timing (see figure 8) intrn (or i/o(7:3)b when used as interrupts) negated from: read rxfifo (rxrdy/ffull interrupt) 40 60 ns write txfifo (txrdy interrupt) 40 60 ns t *ir reset command (delta break change interrupt) 40 60 ns stop c/t command (counter/timer interrupt 40 60 ns read ipcr (delta input port change interrupt) 40 60 ns write imr (clear of change interrupt mask bit(s)) 40 60 ns clock timing (see figure 9) t *clk x1/clk high or low time 30 20 ns f *clk x1/clk frequency (7.0 to 16.2 mhz with crystal) 1 14.7 34 mhz f *ctc c/t clk (ip2) high or low time (c/t external clock input) 30 20 ns f *ctc c/t clk (ip2) frequency 0 8 mhz t *rx rxc high or low time (16x) 30 ns f *rx rxc frequency (16x) 0 24 mhz rxc frequency (1x) 0 1 mhz t *tx txc high or low time (16x) 30 ns f *tx txc frequency (16x) 24 mhz txc frequency (1x) 0 1 mhz transmitter timing (see figure 12) t *txd txd output delay from txc low (txc input pin) 40 60 ns t *tcs output delay from txc output pin low to txd data output 6 30 ns receiver timing (see figure 13) t *rxs rxd data setup time to rxc high 50 40 ns t *rxh rxd data hold time from rxc high 50 40 ns 68000 or motorola bus timing (see figure ___) t dcr dackn low (read cycle) from x1 high 18 25 ns t dcw dackn low (write cycle) from x1 high 18 25 ns t dah dackn high from csn or iackn high 2 5 ns t dat dackn high impedance from csn or iackn high 10 15 ns t csc csn or iackn setup time to x1 high for minimum dackn cycle 15 10
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 61 notes: 1. parameters are valid over specified temperature range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4v and 3.0v with a transitio n time of 5 ns maximum. for x1/clk this swing is between 0.4v and 4.4v. all time measurements are referenced at input voltages of 0.8v and 2.0 v and output voltages of 0.8v and 2.0v, as appropriate. 3. test conditions for outputs: c l = 150 pf, except interrupt outputs. test conditions for interrupt outputs: c l = 50 pf, r l = 2.7k ohm to v cc . 4. typical values are at +25 c, typical supply voltages, and typical processing parameters. 5. timing is illustrated and referenced to the wrn and rdn inputs. also, cen may be the `strobing' input. cen and rdn (also cen and wrn) are ored internally. the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. guaranteed by characterization of sample units. 7. if cen is used as the `strobing' input, the parameter defines the minimum high times between one cen and the next. the rdn si gnal must be negated for t rwd time to guarantee that any status register changes are valid. 8. minimum frequencies are not tested but are guaranteed by design. 9. clocks for 1x mode should be symmetrical. resetn t res sd00133 figure 1. reset timing (80xxx mode) a0a3 cen t as t cs t ch rdn t rw t rwd d0d7 (read) t dd t df float float valid not valid wdn t rwd valid d0d7 (write) t ds t dh t ah sd00087 figure 2. bus timing (80xxx mode) resetn t res sd00109 figure 3. reset timing (68xxx mode)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 62 x1/clk a1a4 rwn csn d0d7 dtackn t csc t as t cs t df t dat t dah t ch t rwd t dd t dcr t ah data valid not valid t da note: dackn low requires two rising edges of x1 clock after csn is low. sd00687 figure 4. bus timing (read cycle) (68xxx mode) x1/clk a1a4 rwn csn d0d7 dtackn t csc t as t cs t dh t dat t dah t ch t rwd t ds t dcw t ah note: dackn low requires two rising edges of x1 clock after csn is low. sd00688 figure 5. bus timing (write cycle) (68xxx mode)
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 63 x1/clk intrn iackn d0d7 dtackn t csc t dd t df t csd t dal t dcr t dah t dat note: dackn low requires two rising edges of x1 clock after csn is low. sd00149 figure 6. interrupt cycle timing (68xxx mode) (b) output pins rdn ip0ip6 wrn op0op7 t ps t ph t pd old data new data (a) input pins sd00135 figure 7. port timing
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 64 notes: 1. intrn or op3-op7 when used as interrupt outputs. 2. the test for open-drain outputs is intended to guarantee switching of the output transistor. measurement of this response is referenced from the midpoint of the switching signal, v m , to a point 0.5v above v ol . this point represents noise margin that assures true switching has occurred. beyond this level, the effects of external cir cuitry and test environment are pronounced and can greatly affect the resultant measurement. v m v ol +0.5v v ol wrn interrupt 1 output t ir v m v ol +0.5v v ol rdn interrupt 1 output t ir sd00136 figure 8. interrupt timing (80xxx mode) c1 = c2 ~ 24pf for c l = 20pf t clk t ctc t rx t tx x1/clk ctclk rxc txc t clk t ctc t rx t tx v cc 470 w x1 x2* clk *note: x2 must be left open. x2 14.7456mhz x1 c1 c2 sc28l92 note: resistor required for ttl input. to uart circuit 50k w to 100k w 3pf 3pf c1 and c2 should be chosen according to the crystal manufacturer's specification. c1 and c2 values will include any parasitic capacitance of the wiring and x1 x2 pins. 2pf 4pf package capacitance approximately 4pf. sd00689 parasitic capacitance parasitic capacitance figure 9. clock timing
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 65 t txd t tcs 1 bit time (1 or 16 clocks) txd txc (input) txc (1x output) sd00138 figure 10. transmitter external clocks t rxs t rxh rxc (1x input) rxd sd00139 figure 11. receiver external clock transmitter enabled txd d1 d2 d3 d4 d6 break txrdy (sr2) wrn d1 d8 d9 d10 d12 start break stop break d11 will not be written to the txfifo ctsn 1 (ip0) rtsn 2 (op0) opr(0) = 1 opr(0) = 1 notes: 1. timing shown for mr2(4) = 1. 2. timing shown for mr2(5) = 1. sd00155 figure 12. transmitter timing
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 66 d1 d2 d8 d9 d10 d11 d12 d13 rxd d12, d13 will be lost due to receiver disable. receiver enabled rxrdy (sr0) ffull (sr1) rxrdy/ ffull (op5) 2 rdn status data d1 status data d2 status data d3 status data d10 d11 will be lost due to overrun overrun (sr4) reset by command rts 1 (op0) opr(0) = 1 notes: 1. timing shown for mr1(7) = 1. 2. shown for opcr(4) = 1 and mr(6) = 0. sd00156 figure 13. receiver timing transmitter enabled txd add#1 txrdy (sr2) wrn mr1(43) = 11 mr1(2) = 1 1 bit 9 d0 0 bit 9 add#2 1 bit 9 master station add#1 mr1(2) = 0 d0 mr1(2) = 1 add#2 rxd add#1 1 bit 9 d0 0 bit 9 add#2 1 bit 9 peripheral station 0 bit 9 0 bit 9 receiver enabled rxrdy (sr0) rdn/wrn mr1(43) = 11 add#1 status data d0 status data add#2 sd00096 figure 14. wake-up mode
philips semiconductors objective specification sc28l202 dual uart 2000 feb 10 67 intrn dackn d0d7 txda/b op0op7 125pf +5v i = 2.4ma 125pf i = 2.4ma v ol return to v cc for a 0 level i = 400 m a v oh return to v ss for a 1 level sd00690 figure 15. test conditions on outputs
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 68 qfp52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm sot379-1
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 69 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1mm sot364-1
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 70 notes
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 2000 feb 10 71 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 02-00 document order number: 9397 750 06826

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

▲Up To Search▲

Price & Availability of SC28L202A1B

	To Download SC28L202A1B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .